Xilinx FPGA

Trainings on Xilinx FPGA and Vivado Design Suite

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F_VBASE Designing FPGAs Using the Vivado Design Suite NEW   4d3200 €
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Description

For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design.

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F_STAXDC Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado NEW   4d3200 €
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Training about XDC Timing constraints (SDC), Static timing analysis, good Xilinx FPGA design practice (UltraFast Design Methodology) and advanced use of the Vivado™ Design Suite

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F_PR Partial Reconfiguration NEW   2d2000 €
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Description

Learn how to build et assembly reconfigurable partitions to configure partially et dynamically a Xilinx™ FPGA

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F_US Designing with the Xilinx™ UltraScale and UltraScale+ Families NEW   2d1600 €
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Description

Learn how to effectively use Xilinx™ Ultrascale and UltraScale+ architectural resources

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F_7SERIE Designing with the Xilinx™ 7-Series Families   2d
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Description

Learn how to effectively use Xilinx™ 7 series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources

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Xilinx SoC & MPSoC

Trainings on Zynq-7000® SoC and Zynq® UltraScale+™ MPSoC and design tools

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E_ZAHS The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components NEW   4d3200 €
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Description

This training is for those who are starting an embedded design based on Zynq™-7000 or Zynq UltraScale+™ MPSoC or even MicroBlaze™. System Architecture, Hardware and Software Design, as well as the use of the tools are covered through theory and exercises on a ZedBoard or ZCU104 board of your choice.

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E_ZADV Zynq-7000™ : Embedded Systems Advanced Design NEW   2d1600 €
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Description

This training explains the more advanced concept used during hardware design of a Zynq™-7000 SoC (AXI debug, AXI-Streaming, memory controlers, DMA and boot process). This training is intended for those who already have experience in architecture and hardware and software development on Zynq-7000 and who wish to confirm and deepen their knowledge.

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E_ZUPSA Zynq UltraScale+™ MPSoC : System Architecture   2d2000 €
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Description

Xilinx components Zynq UltraScale+™ architecture training. This component include a dual/quad ARM® Cortex™-A53MP and a dual ARM® Cortex™-R5MP.

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E_ZUPSW Zynq UltraScale+™ MPSoC : Hardware and Software Design   2d2000 €
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Xilinx components Zynq UltraScale+™ hardware and software design. This component include a dual/quad ARM® Cortex™-A53MP and a dual ARM® Cortex™-R5MP.

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Vivado™ HLx
D_HLS Vivado™ High Level Synthesis   2d1600 €
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Description

Training on the Xilinx™ C to RTL synthesis tool

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PetaLinux™
E_PLNX Embedded Design with Xilinx™ PetaLinux Tools   2d2000 €
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Description

Embedded Linux Xilinx™ distribution (Petalinux) training

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Vitis Xilinx

Trainings on Vitis Unified Software Platform

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Training
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E_VITIS Migrating to the Vitis Embedded Software Development IDE Workshop NEW   1d800 €
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Description

This workshop demonstrates the tools and techniques required for software design and development using the Vitis™ unified software platform. The emphasis of this course is on: Reviewing the basics of using the Vitis platform Migrating existing SDK projects to the Vitis platform Developing software applications using the Vitis platform

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AI_ACCEL Accelerating Applications with the Vitis Unified Environment Software NEW   2d2000 €
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Description

This course learns how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applicationss. Also learn how to run designs on the Xilinx Alveo™ accelerator card using Nimbix Cloud.

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Connectivity

Trainings on FPGA connectivity

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C_TRX Designing with Xilinx Serial Transceivers NEW   2d1600 €
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Description

In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.

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C_PCIE Designing a LogiCore PCI Express system   2d 
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Description

This training explains the Xilinx™ FPGA hardware design using Xilinx™ PCI-e core

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On demand
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003368A Ethernet Bus NEW   2d 
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Description

Any popularization needed to understand an Ethernet network

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On demand
003367A Ethernet & Switching   4d 
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Description

analysis of the Ethernet specification with the OSI model as a guiding light

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On demand

Digital Signal Processing on FPGA

Trainings on Digital Signal Processing application designs

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D_ESS Essential DSP implementation techniques for Xilinx™ FPGAs   2d1600 €
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Description

This training gives you the ability to use efficiently the Xilinx™ FPGAs resources to design Digital Signal Processing algorithm.

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HDL Languages

Trainings on Hardware Description Languages

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L_VHDL VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design NEW   5d2500 €
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Description

Training on Xilinx FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (asynchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis)

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L_VV_UP Upgrading VHDL to Verilog and Verilog to VHDL NEW   2d1600 €
Details
Description

This course is intended for those who master one of the two RTL synthesis languages (VHDL or Verilog) and who wish to understand and/or use the other language (VHDL or Verilog) in their developments.

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