VERSAL Xilinx
Trainings on Xilinx Adaptive SoC Versal™
Reference |
Training |
Duration |
Price |
|||
| ACAP_ARC | Designing with the Versal Adaptive SoC: Architecture and Methodology and NoC NEW | 4d | 4000 € | |||
Details |
DescriptionLearn about Versal® Adaptive SoC architecture and design methodology. Read more |
Dates
Register |
||||
Reference |
Training |
Duration |
Price |
|||
| AIE_INTR | Workshop : AI engines introduction of AMD Xilinx Versal (French Language) 9h - 17h CET NEW | 1d | 0 € | |||
Details |
DescriptionLive Online Workshop Event Read more |
Dates
Register |
||||
| ACAP_AIE | Designing with Versal® AI Engine NEW | 4d | 4000 € | |||
Details |
DescriptionProgram the AI engines, know the system design flow and the interfaces that can be used for data movement. Read more |
Dates
Register |
||||
Vitis Xilinx
Trainings on Vitis Unified Software Platform
Reference |
Training |
Duration |
Price |
|||
| AI_ACCEL | Accelerating Applications with the Vitis Unified Environment Software | 3d | 2700 € | |||
Details |
DescriptionDevelop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications. Read more |
Dates
Register |
||||
Xilinx SoC & MPSoC
Trainings on Zynq-7000® SoC and Zynq® UltraScale+™ MPSoC and design tools
Reference |
Training |
Duration |
Price |
|||
| E_ZAHS | The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components NEW | 4d | 3400 € | |||
Details |
DescriptionLearn system architecture, hardware and software design of Zynq™-7000 and Zynq MPSoC components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104. Read more |
Dates
Register |
||||
Xilinx FPGA
Trainings on Xilinx FPGA and Vivado Design Suite
Reference |
Training |
Duration |
Price |
|||
| F_VBASE | Designing FPGAs Using the Vivado Design Suite | 4d | 3400 € | |||
Details |
DescriptionDesigning an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Read more |
DatesRegister |
||||
| F_STAXDC | Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado | 4d | 3400 € | |||
Details |
DescriptionUnderstand XDC Timing constraints, Static timing analysis, good Xilinx FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite Read more |
Dates
Register |
||||
| F_DFX | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite NEW | 3d | 2700 € | |||
Details |
DescriptionLearn how to build et assembly reconfigurable partitions to configure partially et dynamically a Xilinx™ component Read more |
Dates
Register |
||||
Reference |
Training |
Duration |
Price |
|||
| F_US | Designing with the Xilinx™ UltraScale and UltraScale+ Families | 2d | 2000 € | |||
Details |
DescriptionLearn how to effectively use Xilinx™ Ultrascale and UltraScale+ architectural resources Read more |
DatesRegister |
||||
| F_7SERIE | Designing with the Xilinx™ 7-Series Families | 2d | 2000 € | |||
Details |
DescriptionLearn how to effectively use Xilinx™ 7 series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources Read more |
DatesRegister |
||||
Digital Signal Processing on RFSoC and FPGA
Trainings on Digital Signal Processing application designs on RFSoC and FPGA
Reference |
Training |
Duration |
Price |
|||
| C_RFSOC | Designing with the Zynq UltraScale+ RFSoC NEW | 3d | ||||
Details |
DescriptionThis course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks. Read more |
DatesOn demand |
||||
Connectivity
Trainings on FPGA connectivity
HDL Languages
Trainings on Hardware Description Languages
Reference |
Training |
Duration |
Price |
|||
| L_VHDL | VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design | 5d | 3000 € | |||
Details |
DescriptionTraining on Xilinx FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (asynchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis) Read more |
Dates
Register |
||||