Xilinx FPGA

Trainings on Xilinx FPGA and Vivado Design Suite

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Training
Duration
Price
F_VDM Vivado™ Design Suite : UltraFast Design Methodology   2d1600 €
Details
Description

This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software.

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F_PR Vivado™ Design Suite : Partial Reconfiguration   2d1600 €
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Description

Learn how to build et assembly reconfigurable partitions to configure partially et dynamically a Xilinx™ FPGA

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F_STAXDC Vivado™ Design Suite : Static Timing Analysis and Xilinx Design Constraints NEW   3d2000 €
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Description

Training about XDC Timing constraints (SDC), Static timing analysis, and good Xilinx FPGA design practice using Vivado™ Design Suite

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F_VDES12 Designing FPGAs Using the Vivado Design Suite 1 & 2   4d2900 €
Details
Description

2 SUJETS en 1 FORMATION.For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design, how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

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F_VDES1 Designing FPGAs Using the Vivado Design Suite 1   2d1600 €
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Description

For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design.

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F_VDES2 Designing FPGAs Using the Vivado Design Suite 2   2d1600 €
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Description

This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

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F_VDES34 Designing FPGAs Using the Vivado Design Suite 3 & 4   4d2900 €
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Description

2 SUJETS en 1 FORMATION. This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains. This course tackles the most sophisticated aspects of the Vivado® Design Suite and Xilinx hardware, and enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

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F_VDES3 Designing FPGAs Using the Vivado Design Suite 3   2d1600 €
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Description

This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

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F_VDES4 Designing FPGAs Using the Vivado Design Suite 4   2d1600 €
Details
Description

This course tackles the most sophisticated aspects of the Vivado® Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

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Training
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F_US Designing with the Xilinx™ UltraScale and UltraScale+ Families NEW   2d1600 €
Details
Description

Learn how to effectively use Xilinx™ Ultrascale and UltraScale+ architectural resources

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F_7SERIE Designing with the Xilinx™ 7-Series Families   2d1600 €
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Description

Learn how to effectively use Xilinx™ 7 series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources

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F_V6 Designing with the Virtex-6 Family   2d 
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Description

Learn how to effectively utilize Xilinx™ Virtex®-6 architectural resources

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On demand
F_S6 Designing with the Spartan-6 Family   2d 
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Description

Learn how to effectively utilize Xilinx™ Spartan®-6 architectural resources

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Dates
On demand
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Training
Duration
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F_V4ISEx Vivado™ Design Suite, Advanced XDC and Static Timing Analysis for ISE® Users (2 in 1) NEW   4d2900 €
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Description

2 THEMES in 1 TRAINING. Vivado™ Design Suite training, Advanced XDC and Static Timing Analysis for people who wants an update from ISE® Software Project Navigator

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F_V4ISE Vivado™ Design Suite for ISE® Software Project Navigator Users   2d1600 €
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Description

Vivado™ Design Suite overview for people who wants an update from ISE® Software Project Navigator

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F_VAXDC4 Vivado™ Design Suite : Advanced XDC and Static Timing Analysis for ISE® Software Users   2d1600 €
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Description

Vivado™ Design Suite training for people who want an update from ISE® Design Suite and PlanAhead™. A first experience with Vivado™ Design Suite is highly requested.

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Xilinx SoC & MPSoC

Trainings on Zynq-7000® SoC and Zynq® UltraScale+™ MPSoC and design tools

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Training
Duration
Price
E_ZAHS The essentials of embedded design for Xilinx components NEW   4d3200 €
Details
Description

Zynq™-7000 : System Architecture, Hardware and Software Design (3 in 1)

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E_ZSA Zynq™ : System Architecture   2d 
Details
Description

Xilinx components Zynq-7000 architecture training. This component include a dual ARM® Cortex™-A9MP.

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On demand
E_HW Zynq™ : Embedded Systems Hardware Design   2d 
Details
Description

Training about Zynq™-7000 hardware design using Vivado™ IP integrator including creation and integration of custom IP

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On demand
E_SW Zynq™ : Embedded Systems Software Design   2d 
Details
Description

Training about Zynq™-7000 software design using Xilinx® SDK including creation and integration of custom driver, interrupt handling, software debug, application profiling, memory management

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On demand
E_HWADV Zynq™ : Embedded Systems Advanced Hardware Design   2d1600 €
Details
Description

This training explains the more advanced concept used during hardware design of a Zynq™-7000 SoC (AXI debug, AXI-Streaming, memory controlers, DMA and boot process)

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E_SWADV Zynq™ : Embedded Systems Advanced Software Design   1d1000 €
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Description

This training explains the more advanced concept used during software design of a Zynq™-7000 SoC including high-speed peripheral (Ethernet, USB), DMA and boot process

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Training
Duration
Price
E_ZUPSA Zynq UltraScale+™ MPSoC : System Architecture   2d2000 €
Details
Description

Xilinx components Zynq UltraScale+™ architecture training. This component include a dual/quad ARM® Cortex™-A53MP and a dual ARM® Cortex™-R5MP.

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E_ZUPHW Zynq UltraScale+™ MPSoC : Hardware Design   1d1200 €
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Description

Xilinx components Zynq UltraScale+™ hardware design. This component include a dual/quad ARM® Cortex™-A53MP and a dual ARM® Cortex™-R5MP.

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E_ZUPSW Zynq UltraScale+™ MPSoC : Hardware and Software Design   2d2000 €
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Description

Xilinx components Zynq UltraScale+™ hardware and software design. This component include a dual/quad ARM® Cortex™-A53MP and a dual ARM® Cortex™-R5MP.

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Training
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SDSoC™
E_SDSOCx SDSoC Development Environment and Methodology and Advanced Training (2 in 1) NEW   3d2500 €
Details
Description

Training on the Xilinx™ SDSoC tools including tool flow to create accelerated systems and methodology, employ SDSoC™ development environment optimization techniques to create high-performance, accelerated systems.

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E_SDSOC SDSoC Development Environment and Methodology   1d1200 €
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Description

Training on the Xilinx™ SDSoC tools including tool flow to create accelerated systems and methodology

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E_ADVSDS Advanced SDSoC Development Environment and Methodology   2d2000 €
Details
Description

This course is structured to help designers employ SDSoC™ development environment optimization techniques to create high-performance, accelerated systems.

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Vivado™ HLx
D_HLS Vivado™ High Level Synthesis   2d1600 €
Details
Description

Training on the Xilinx™ C to RTL synthesis tool

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PetaLinux™
E_PLNX Embedded Design with Xilinx™ PetaLinux Tools   2d 
Details
Description

Embedded Linux Xilinx™ distribution (Petalinux) training

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Dates
On demand

Connectivity

Trainings on FPGA connectivity

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Training
Duration
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C_TRX Designing with Xilinx Serial Transceivers NEW   2d1600 €
Details
Description

In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.

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C_MGTUS Designing with UltraScale FPGA Transceivers   2d 
Details
Description

Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.

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On demand
C_MGT Designing with Multi-Gigabit Serial I/O   3d 
Details
Description

Learn how to employ serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.

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On demand
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Duration
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C_PCIE Designing a LogiCore PCI Express system   2d 
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Description

This training explains the Xilinx™ FPGA hardware design using Xilinx™ PCI-e core

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On demand
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Training
Duration
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003368A Ethernet Bus NEW   2d1500 €
Details
Description

Any popularization needed to understand an Ethernet network

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003367A Ethernet & Switching   4d 
Details
Description

analysis of the Ethernet specification with the OSI model as a guiding light

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On demand

Digital Signal Processing on FPGA

Trainings on Digital Signal Processing application designs

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Training
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D_ESS Essential DSP implementation techniques for Xilinx™ FPGAs   2d 
Details
Description

This training gives you the ability to use efficiently the Xilinx™ FPGAs resources to design Digital Signal Processing algorithm.

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On demand

HDL Languages

Trainings on Hardware Description Languages

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Training
Duration
Price
L_VHDL VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design NEW   5d2500 €
Details
Description

Training on Xilinx FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (asynchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis)

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