ACAP Xilinx

Trainings on Xilinx ACAP Versal™

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A_START Workshop : Getting Started with Xilinx Versal ACAP Platform (French Language) 9h - 17h CET NEW   1d500 €
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Live Online Workshop Event

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ACAP_ARC Designing with the Versal ACAP: Architecture and Methodology and NoC NEW   4d4000 €
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Learn about Versal® ACAP architecture and design methodology.

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ACAP_AIE Designing with Versal® AI Engine NEW   4d4000 €
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Description

Program the AI engines, know the system design flow and the interfaces that can be used for data movement.

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Vitis Xilinx

Trainings on Vitis Unified Software Platform

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Training
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E_VITIS Workshop : Start with Vitis tool (French Language) 9h - 17h CET   1d1000 €
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Live Online Workshop Event

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AI_ACCEL Accelerating Applications with the Vitis Unified Environment Software   3d2700 €
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Develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications.

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D_HLS Vitis™ High Level Synthesis   2d2000 €
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Description

Enhance productivity using the Vitis™ HLS tool

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Xilinx SoC & MPSoC

Trainings on Zynq-7000® SoC and Zynq® UltraScale+™ MPSoC and design tools

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E_ZAHS The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components NEW   4d3400 €
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Description

Learn system architecture, hardware and software design of Zynq™-7000 and Zynq MPSoC components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104.

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E_ZUPAHS Zynq UltraScale+™ MPSoC : System Architecture, Hardware and Software Design NEW   4d3400 €
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Description

Understand Xilinx components Zynq UltraScale+™ architecture, hardware and software design.

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E_PLNX Embedded Design with Xilinx™ PetaLinux Tools   3d2700 €
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Learn how to use the PetaLinux tool to create an embedded Linux distribution

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Xilinx FPGA

Trainings on Xilinx FPGA and Vivado Design Suite

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Training
Duration
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F_VBASE Designing FPGAs Using the Vivado Design Suite   4d3400 €
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Description

Designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design.

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F_STAXDC Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado   4d3400 €
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Description

Understand XDC Timing constraints, Static timing analysis, good Xilinx FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite

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F_DFX Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite NEW   3d2700 €
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Description

Learn how to build et assembly reconfigurable partitions to configure partially et dynamically a Xilinx™ component

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F_US Designing with the Xilinx™ UltraScale and UltraScale+ Families   2d2000 €
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Learn how to effectively use Xilinx™ Ultrascale and UltraScale+ architectural resources

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F_7SERIE Designing with the Xilinx™ 7-Series Families   2d2000 €
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Learn how to effectively use Xilinx™ 7 series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources

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Digital Signal Processing on RFSoC and FPGA

Trainings on Digital Signal Processing application designs on RFSoC and FPGA

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C_RFSOC Designing with the Zynq UltraScale+ RFSoC NEW   3d 
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Description

This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.

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D_ESS Essential DSP implementation techniques for Xilinx™ FPGAs   2d2000 €
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Description

Understand and effectively use the resources of Xilinx™ FPGAs for implementing digital signal processing algorithms.

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Connectivity

Trainings on FPGA connectivity

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C_TRX Designing with Xilinx Serial Transceivers   2d2000 €
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Description

Learn how to use serial transceivers in your UltraScale ™, UltraScale + ™ FPGA or Zynq® UltraScale + MPSoC.

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C_PCIE Designing an Integrated PCI Express System   2d2000 €
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Description

Understand the Xilinx™ FPGA hardware design using Xilinx™ PCI-e core

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HDL Languages

Trainings on Hardware Description Languages

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Training
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L_VHDL VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design   5d3000 €
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Description

Training on Xilinx FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (asynchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis)

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L_VV_UP Upgrading VHDL to Verilog and Verilog to VHDL   2d2000 €
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Description

Understand and/or use the other language (VHDL or Verilog) in their developments.

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