AMD Versal™
Trainings on Adaptive SoC Versal™
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| A_QSTART | Quick Start : Designing with AMD Versal™ Adaptive SoC (French Language) 9h - 17h CET NEW | 1 day | 0 € | |||
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DescriptionLive Online Workshop Event Read more |
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| ACAP_NOC | Workshop : Designing with the Network On Chip of AMD Versal (French Language) 9h - 17h CET NEW | 1 day | 900 € | |||
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DescriptionThis course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device. Read more |
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| ACAP_ARC | Designing with the Adaptive SoC Versal™ : Architecture and Methodology NEW | 4 days | 3600 € | |||
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DescriptionLearn about Versal™ architecture and design methodology. Read more |
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| AIE_INTR | Workshop : Designing with AMD Versal™ AI Engine: Quick Start (French Language) 9h - 17h CET NEW | 1 day | 900 € | |||
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DescriptionLive Online Workshop Event Read more |
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| ACAP_AIE | Designing with Versal™ AI Engine NEW | 4 days | 3600 € | |||
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DescriptionProgram the AI engines, know the system design flow and the interfaces that can be used for data movement. Read more |
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AMD Vitis™
Trainings on Vitis Unified Software Platform
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| AI_ACCEL | Accelerating Applications with the Vitis™ Unified Environment Software | 3 days | 3000 € | |||
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DescriptionDevelop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications. Read more |
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AMD SoCs
Trainings on Zynq-7000™ SoC and Zynq MPSoC™ and design tools
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| E_ZAHS | The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components NEW | 4 days | 3600 € | |||
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DescriptionLearn system architecture, hardware and software design of Zynq™-7000, Zynq™ MPSoC and Versal™ components, and tool usage through theory and exercises on your choice of ZedBoard or ZCU104. Read more |
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AMD FPGA
Trainings on AMD FPGA and Vivado™ Design Suite
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| F_VBASE | Designing FPGAs Using the Vivado™ | 4 days | 3600 € | |||
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DescriptionDesigning an FPGA design, which includes creating a Vivado™ Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Read more |
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| F_STAXDC | Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™ | 4 days | 3600 € | |||
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DescriptionUnderstand XDC Timing constraints, Static timing analysis, good AMD FPGA design practice, advanced debug methods and advanced use of the Vivado™ Design Suite Read more |
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| F_DFX | Designing with Dynamic Function eXchange (DFX) Using the Vivado™ NEW | 3 days | 3000 € | |||
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DescriptionLearn how to build et assembly reconfigurable partitions to configure partially et dynamically a AMD component Read more |
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| F_US | Designing with the AMD UltraScale™ and UltraScale+™ Families | 2 days | 2200 € | |||
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DescriptionLearn how to effectively use AMD Ultrascale™ and UltraScale+™ architectural resources Read more |
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| F_7SERIE | Designing with the AMD 7-Series Families | 2 days | ||||
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DescriptionLearn how to effectively use AMD7-series (Spartan-7, Artix-7, Kintex-7 and Virtex-7) architectural resources Read more |
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Digital Signal Processing on RFSoC and FPGA
Trainings on Digital Signal Processing application designs on RFSoC and FPGA
Connectivity
Trainings on FPGA connectivity
HDL Languages
Trainings on Hardware Description Languages
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| L_VHDL | VHDL Logical Synthesis and Simulation for AMD FPGA design | 5 days | 4400 € | |||
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DescriptionUnderstand AMD FPGA global architecture, VHDL Logical Synthesis and Simulation for Xilinx FPGA, fundamentals methodology (synchronism, IP Catalog, basic constraints - timing, IOs -, static timing analysis) Read more |
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