Upgrading VHDL to Verilog and Verilog to VHDL

(ref.L_VV_UP)

2 days - 14 hours

Objectives

  • Understanding the differences between VHDL and Verilog
  • Understanding the multiple possibilities offered by VHDL and Verilog languages
  • Know the instruction sets for RTL synthesis
  • Know the instruction sets for the simulation

Partners

xilinx atp

Prerequisites

  • This course is intended for electronic engineers who already have a good knowledge of digital electronic circuit design, and who master one of the RTL logic synthesis languages (VHDL or Verilog), and who wish to acquire additional knowledge of the second RTL logic synthesis language (VHDL or Verilog).

Configurations

  • Software Configuration :
    • Vivado Design Suite 2020.2
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080

Outline

Rules for writing VHDL/Verilog code in logical synthesis

  • Concept of entity/architecture
  • Predefined objects and types
  • Competing Instructions
  • Sequential instructions

Hierarchy management for better reuse

  • Notions of variables and examples of use
  • Generality and automatic parameterization of reusable modules
  • Predefined Attributes Useful in Logical Synthesis
  • Functions and procedures
  • Definition of packages and libraries

Testbenches and simulation

  • Some basic rules for writing an efficient testbench
  • Simulation-specific instructions
  • Writing component models to make simulation more realistic
  • Writing and reading ASCII files
  • Generation of information messages

Teaching Methods

  • Classroom training:
    • Face to face
    • Presentation by video projector
    • Provision of PDF course materials
  • Virtual training:
    • Onlive training
    • Presentation by Webex
    • Provision of PDF course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics