Upgrading VHDL to Verilog and Verilog to VHDL


2 days - 14 hours


  • Understanding the differences between VHDL and Verilog
  • Understanding the multiple possibilities offered by VHDL and Verilog languages
  • Know the instruction sets for RTL synthesis
  • Know the instruction sets for the simulation


xilinx atp


  • This course is intended for electronic engineers who already have a good knowledge of digital electronic circuit design, and who master one of the RTL logic synthesis languages (VHDL or Verilog), and who wish to acquire additional knowledge of the second RTL logic synthesis language (VHDL or Verilog).


  • Software Configuration :
    • Xilinx Vivado™ Design Edition 2019.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080


Rules for writing VHDL/Verilog code in logical synthesis

  • Concept of entity/architecture
  • Predefined objects and types
  • Competing Instructions
  • Sequential instructions

Hierarchy management for better reuse

  • Notions of variables and examples of use
  • Generality and automatic parameterization of reusable modules
  • Predefined Attributes Useful in Logical Synthesis
  • Functions and procedures
  • Definition of packages and libraries

Testbenches and simulation

  • Some basic rules for writing an efficient testbench
  • Simulation-specific instructions
  • Writing component models to make simulation more realistic
  • Writing and reading ASCII files
  • Generation of information messages

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics