Designing with Versal™ Gen1 & Gen2 : Architecture, Tools and Methodology

(ref.VER_ARC)
TIME

4 days - 28 hours   

Target objectives and skills

  • 1 - Describe the architecture of Versal at a high level.
  • 2 - Describe the different engines of the Versal device
  • 3 - Use the different blocks of the Versal architecture to create complex systems
  • 4 - Describe the boot
  • 5 - Build an application for AI engines
  • 6 - Describe GT links, the PCIe and multimedia block, and be familiar with design tools
  • 7 - Describe debugging methods and power consumption and dissipation issues

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • People with disabilities may have special training needs. Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability. Don't hesitate to to discuss your requirements.agefiph

Prerequisites

  • Comfort with the C/C++ programming language
  • Vitis™ IDE software development flow
  • Hardware development flow with the Vivado® Design Suite
  • Basic knowledge of UltraScale™/UltraScale+™ FPGAs and Zynq™ UltraScale+ MPSoCs

Course content

Day 1

Objective 1

  • Introduction & Portfolio {Lecture}
  • Architecture Gen1 & Gen2 Overview {Lecture}

Objective 2

  • Processing System Gen1 & Gen2 {Lecture}
  • Programmable Logic (PL) {Lecture}
  • DSP Engine {Lecture}
  • AI, AI-ML, AI-MLv2 Engine {Lecture}
  • NoC Introduction and Concepts {Lecture, Lab}
  • Design Tool Flow {Lecture, Lab}

Day 2

Objective 3

  • IO Resources {Lecture}
  • Clocking Architecture {Lecture}
  • Memory Solutions {Lecture}
  • NoC DDR4 & NoC2 DDR5 Memory Controller {Lecture, Lab}

Objective 4

  • Platform Management Controller (PMC) {Lecture}
  • Boot and Configuration {Lecture, Lab}

Day 3

Objective 5

  • AI Engine Programming: Kernels and Graphs {Lecture, Lab}
  • AI Engine System Partitioning {Lecture}

Objective 6

  • Serial Transceivers {Lecture}
  • PCI Express solutions {Lecture}
  • Multimedia Hard Blocks (Gen2) {Lecture}
  • Platform Development Methodology {Lecture, Lab}

Day 4

Objective 6

  • System Simulation {Lecture, Lab}
  • Vitis export to Vivado Flow {Lab}

Objective 7

  • Configuration and Debugging {Lecture}
  • Hard Block Debug {Lecture}
  • Fabric Debug {Lecture, Lab}
  • Power Design Manager {Lecture}
  • Power and Thermal Solutions {Lecture}

Teaching methods and support - Assessment and recognition

  • Teaching methods :
    • Alternating lectures, technical questionnaires and exercises on individual machines.
  • Pedagogical follow-up :
    • Signed attendance sheet
  • Pedagogical assessment :
    • Continuous assessment and progress sheet :
      • Technical questionnaire
      • Practical work results
      • Validation of objectives
  • Satisfaction survey :
    • At the end of training: assessment form completed by the trainee
    • At 3 months: evaluation form completed by the trainee after application to the company
  • Certificate :
    • Training certificate with assessment of learning provided to trainee
    • Certificate of completion provided to employer

Teaching Methods

  • Inter-company online training :
    • Fast Internet connection, webcam, headset
    • Presentation by Webex by Cisco Webex de Cisco
    • Provision of course material in PDF format
    • Labs on individual Cloud PC by RealVNC REALVNC
  • Intra-company face-to-face training on customer site : (details to be confirmed prior to training)
    • Suggested supply by the customer :
      • Training room
      • Video projector
      • Whiteboard
      • Individual PC with AMD tools
    • Provided by MVD Training :
      • Course material in PDF format
      • Practical work on individual PCs (loan of equipment available on request)

Recommended computer hardware

  • Inter-company online training :
    • Recent computer OS Linux or Windows 64-bits
    • Fast Internet, webcam, headset
    • Software tool WebEx Cisco
    • AMD remote tools :
    • AMD local tools :
      • Software tool AMD Vitis & Vivado
  • Face-to-face training on customer site :
    • Recent computer OS Linux or Windows 64-bits
    • Software tool AMD Vitis & Vivado

Teaching staff

  • William Duluc, Electronics and Telecoms Engineer, AMD Expert since 2009 and AMD Trainer since 2017 :
    • Expert AMD FPGA - Language VHDL/Verilog - RTL Design
    • Expert AMD SoC & MPSoC - Language C/C++ - System Design
    • Expert DSP & AMD RFSoC – HLS - Matlab - Design DSP RF
    • Expert AMD Versal – AI Engines – Heteregenous System Architect

Certified Partner

xilinx atp

Notes

  • Release date: 09/10/2025