Designing with the Xilinx™ 7-Series Families
(ref.F_7SERIE)
2 days - 14 hours
Objectives
- After completing this training, you will have the necessary skills to:
- 1- Describe the new CLB capabilities and the impact that they make on your HDL coding style
- 2- Define the block RAM, FIFO, and DSP resources available
- 3 - Properly design for the I/O and SERDES resources
- 4 - Identify the MMCM, PLL, and clock routing resources
- 5 - Describe the hard resources available (DDR3, transceivers, ...)
Prerequisites
- Basic knowledge FPGAs architectures
- A successful first experience of designing an VHDL–based FPGA
Concerned public
- Technicians and Engineers in Digital Electronics
- All our training courses are given at a distance and are accessible to people with reduced mobility.
- Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability.
Notes
- Release date: 20/12/2021
Chapters
Objective 1
- 7 Series FPGA Overview {Lecture}
- CLB Architecture {Lecture}
- Slice Flip-Flops {Lecture}
- HDL Coding Techniques {Lecture, Lab}
Objective 2
- Block RAM Memory Resources {Lecture, Lab}
- FIFO Memory Resources {Lecture}
- DSP Resources {Lecture, Lab}
Objective 3
- I/O Resources Overview {Lecture}
- I/O Electrical Resources {Lecture}
- I/O Logical Resources {Lecture, Lab}
Objective 4
- Clocking Resources {Lectures, Lab}
Objective 5
- Memory Controllers {Lecture}
- Transceivers {Lecture}
- Dedicated Hardware {Lecture}
Teaching Methods
- Inter-company online training :
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
- Expert SoC & MPSoC XILINX - Language C/C++ - System Design
- Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
- Expert ACAP XILINX – AI Engines – Heteregenous System Architect
PC Recommended
- Software Configuration :
- Hardware configuration:
- Recent computer (i5 or i7)
- OS Linux 64-bits (Windows 10 compatible)
- At least 16GB RAM
- Display resolution recommended 1920x1080