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    • ACAP Xilinx
      • Versal® Architecture & NOC
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    • Vitis Xilinx
      • Accelerating Applications with the Vitis
      • High-Level Synthesis with the Vitis HLS Tool
    • Xilinx SoC & MPSoC
      • SoC Zynq-7000®
      • MPSoC Zynq® UltraScale+™
      • PetaLinux™
    • Xilinx FPGA
      • Vivado Design Suite
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
      • DSP Functions
    • Connectivity
      • Multi-Gigabit Transceivers
      • PCI Express
    • HDL Languages
      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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MVD Training

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Up coming training sessions

Designing with the Versal ACAP: Architecture and Methodology and NoC

April 03-06[register]

EN LIGNE

Designing with Versal® AI Engine

April 17-20[register]

EN LIGNE

The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components

May 02-05[register]

EN LIGNE

Training sessions schedule

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Xilinx ACAP

Xilinx ACAP

Versal ACAPs

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Vitis Xilinx

Vitis Xilinx

Vitis Unified Software Platform

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Xilinx SoC

Xilinx SoC

Zynq, Zynq MPSoC, HLx, PetaLinux

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Xilinx FPGA

Xilinx FPGA

Ultrascale, Vivado, 7-Serie,...

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DSP

RFSoC & DSP

Digital Signal Processing on RFSoC and FPGA

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Connectivity

Connectivity

Transceivers, PCI-e

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HDL language

HDL language

Hardware Description Language

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