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      • Workshop : Start with Versal™
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      • High-Level Synthesis with the Vitis HLS Tool
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      • Vivado Design Suite
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
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      • Upgrading VHDL to Verilog and Verilog to VHDL
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MVD Training

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Up coming training sessions

VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design

October 25-29[register]

EN LIGNE

Designing FPGAs Using the Vivado Design Suite

October 05-08[register]

EN LIGNE

Designing an Integrated PCI Express System

October 18-19[register]

EN LIGNE

Zynq UltraScale+™ MPSoC : Hardware and Software Design

October 22-23[register]

EN LIGNE

Training sessions schedule

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Xilinx ACAP

Xilinx ACAP

Versal ACAPs

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Vitis Xilinx

Vitis Xilinx

Vitis Unified Software Platform

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Xilinx SoC

Xilinx SoC

Zynq, Zynq MPSoC, HLx, PetaLinux

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Xilinx FPGA

Xilinx FPGA

Ultrascale, Vivado, 7-Serie,...

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DSP

RFSoC & DSP

Digital Signal Processing on RFSoC and FPGA

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Connectivity

Connectivity

Transceivers, PCI-e, Ethernet

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HDL language

HDL language

Hardware Description Language

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