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    • AMD Versal™
      • Versal™ Architecture, NoC and methodology
      • Versal™ AI Engine
    • AMD Vitis™
      • Software design of embedded systems with the Vitis tool
      • Accelerating Applications with the Vitis
      • High-Level Synthesis with the Vitis HLS Tool
    • AMD SoCs
      • Embedded design for AMD SoCs
      • MPSoC Zynq™ UltraScale+
      • PetaLinux™
    • AMD FPGA
      • AMD Vivado™
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
      • DSP Functions
    • Connectivity
      • Multi-Gigabit Transceivers
      • PCI Express
    • HDL Languages
      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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PLANNING

Check out our training schedule

Up coming training sessions

Designing FPGAs Using the Vivado™

October 27-30[register]

Lieu : EN LIGNE ---- CONFIRMATION EN ATTENTE

Accelerating Applications with the Vitis™ Unified Environment Software

November 12-14[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

The essentials of embedded design for Xilinx Zynq™-7000, Zynq™ MPSoC and Versal™ components

November 24-27[register]

Lieu : EN LIGNE ---- CONFIRMATION EN ATTENTE

Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado™

December 08-11[register]

Lieu : EN LIGNE ---- SESSION CONFIRMEE

AMD Versal™

AMD Versal™

Versal™ Adaptive SoC

+
AMD Vitis™

AMD Vitis™

Vitis™ Unified Software Platform

+
AMD SoC

AMD SoC

Zynq™, Zynq™ MPSoC, PetaLinux

+
AMD FPGA

AMD FPGA

UltraScale™, Vivado™, 7-Serie™,...

+
DSP

RFSoC & DSP

Digital Signal Processing on Zynq™ RFSoC and FPGA

+
Connectivity

Connectivity

Transceivers, PCI-e

+
HDL language

HDL language

Hardware Description Language

+

INTRA TRAINING on demand

ACCESS TIME: 2 MONTHS
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CERTIFICATE

QUALIOPI

CUSTOMER SATISFACTION

SATISFACTION

2024 : 94.7%

(115 Attendees)

2023 : 91.8%

(97 Attendees)

2022 : 94.1%

(172 Attendees)
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