MVD TRAINING

Logo du site MVD Training

Authorized Training Xilinx Center

Xilinx Technology Expert

fr eng
  • Homepage
  • Training
    • Presentation
    • ACAP Xilinx
      • Workshop : Start with Versal®
      • Versal® Architecture & NOC
      • Versal® AI Engine
    • Vitis Xilinx
      • Workshop : Start with Vitis tool
      • Accelerating Applications with the Vitis
      • High-Level Synthesis with the Vitis HLS Tool
    • Xilinx SoC & MPSoC
      • SoC Zynq-7000®
      • MPSoC Zynq® UltraScale+™
      • PetaLinux™
    • Xilinx FPGA
      • Vivado Design Suite
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
      • DSP Functions
    • Connectivity
      • Multi-Gigabit Transceivers
      • PCI Express
    • HDL Languages
      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
  • Planning
  • Pre-Registration
  • About Us
    • Presentation
    • Contact
    • Terms of Sale
    • Welcome booklet

MVD Training

Check out our training schedule Ask us for customized training

‹ ›

Up coming training sessions

The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components

May 30-June 02[register]

EN LIGNE

Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

July 04-06[register]

EN LIGNE

Designing with Versal® AI Engine

July 18-21[register]

EN LIGNE

Designing with the Versal ACAP: Architecture and Methodology and NoC

July 18-21[register]

EN LIGNE

Training sessions schedule

+

Xilinx ACAP

Xilinx ACAP

Versal ACAPs

+
Vitis Xilinx

Vitis Xilinx

Vitis Unified Software Platform

+
Xilinx SoC

Xilinx SoC

Zynq, Zynq MPSoC, HLx, PetaLinux

+
Xilinx FPGA

Xilinx FPGA

Ultrascale, Vivado, 7-Serie,...

+
DSP

RFSoC & DSP

Digital Signal Processing on RFSoC and FPGA

+
Connectivity

Connectivity

Transceivers, PCI-e

+
HDL language

HDL language

Hardware Description Language

+
  • Homepage
  • About Us
  • Contact
  • Terms of Sale

MVD Training © 2021