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    • ACAP Xilinx
      • Start with Versal™
      • Versal™ Architecture
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      • Accelerating Applications with the Vitis
    • Xilinx SoC & MPSoC
      • SoC Zynq-7000®
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      • Vivado Design Suite
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
      • DSP Functions
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      • Multi-Gigabit Transceivers
      • PCI Express
      • Ethernet
    • HDL Languages
      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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MVD Training

Check out our training schedule Ask us for customized training

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Up coming training sessions

Getting Started with Xilinx Versal ACAP Platform (FREE)

March 25-26[register]

Webex

The essentials of embedded design for Xilinx Zynq™-7000 & Zynq MPSoC components

March 09-12[register]

SEVRES (92)

Vivado™ High Level Synthesis

March 15-16[register]

EN LIGNE

Accelerating Applications with the Vitis Unified Environment Software

March 17-18[register]

EN LIGNE

Training sessions schedule

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Xilinx ACAP

Xilinx ACAP

Versal ACAPs

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Vitis Xilinx

Vitis Xilinx

Vitis Unified Software Platform

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Xilinx SoC

Xilinx SoC

Zynq, Zynq MPSoC, HLx, PetaLinux

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Xilinx FPGA

Xilinx FPGA

Ultrascale, Vivado, 7-Serie,...

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DSP

RFSoC & DSP

Digital Signal Processing on RFSoC and FPGA

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Connectivity

Connectivity

Transceivers, PCI-e, Ethernet

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HDL language

HDL language

Hardware Description Language

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