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    • AMD Versal™
      • Versal™ Architecture, NoC and methodology
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      • Software design of embedded systems with the Vitis tool
      • Accelerating Applications with the Vitis
      • High-Level Synthesis with the Vitis HLS Tool
    • AMD SoCs
      • Embedded design for AMD SoCs
      • MPSoC Zynq™ UltraScale+
      • PetaLinux™
    • AMD FPGA
      • AMD Vivado™
      • Architecture Advanced training
    • Digital Signal Processing on RFSoC and FPGA
      • Designing with the Zynq UltraScale+ RFSoC
      • DSP Functions
    • Connectivity
      • Multi-Gigabit Transceivers
      • PCI Express
    • HDL Languages
      • VHDL
      • Upgrading VHDL to Verilog and Verilog to VHDL
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Up coming training sessions

Quick Start : Designing with AMD Versal™ Adaptive SoC (French Language) 9h - 17h CET

October 11[register]

EN LIGNE

Upgrading VHDL to Verilog and Verilog to VHDL

October 23-24[register]

EN LIGNE

Designing FPGAs Using the Vivado™

October 28-31[register]

EN LIGNE

VHDL Logical Synthesis and Simulation for AMD FPGA design

November 04-08[register]

EN LIGNE

AMD Versal™

AMD Versal™

Versal™ Adaptive SoC

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AMD Vitis™

AMD Vitis™

Vitis™ Unified Software Platform

+
AMD SoC

AMD SoC

Zynq™, Zynq™ MPSoC, PetaLinux

+
AMD FPGA

AMD FPGA

UltraScale™, Vivado™, 7-Serie™,...

+
DSP

RFSoC & DSP

Digital Signal Processing on Zynq™ RFSoC and FPGA

+
Connectivity

Connectivity

Transceivers, PCI-e

+
HDL language

HDL language

Hardware Description Language

+

PLANNING

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