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MVD Training

Check out our training schedule Ask us for customized training

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Up coming training sessions

Migrating to the Vitis Embedded Software Development IDE Workshop

September 28[register]

ONLINE

VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design

October 12-16[register]

FORMATION EN LIGNE

Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado

November 17-20[register]

FORMATION EN LIGNE

Zynq UltraScale+™ MPSoC : Hardware and Software Design

December 07-08[register]

FORMATION EN LIGNE

Training sessions schedule

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Xilinx FPGA

Xilinx FPGA

Ultrascale, Vivado, 7-Serie,...

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Xilinx SoC & MPSoC

Xilinx SoC & MPSoC

Zynq, SDSoC, HLx, ...

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Vitis Xilinx

Vitis Xilinx

Vitis Unified Software Platform

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Connectivity

Connectivity

Transceivers, PCI-e, Ethernet

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DSP

DSP

Digital Signal Processing

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HDL language

HDL language

Hardware Description Language

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