Designing with the Versal ACAP: Network On Chip
(ref.ACAP_NOC)
1 day - 7 hours
Objectives
- After completing this comprehensive training, you will have the necessary skills to:
- Identify the major network on chip components in the Versal ACAP
- Include the necessary components to access the NoC from the PL
- Configure connection QoS for efficient data movement
Partners
Prerequisites
- Any Xilinx device architecture class
- Familiarity with the Vivado® Design Suite
Configurations
- Software Configuration :
- Vivado Design Suite 2020.2
- Hardware configuration:
- Recent computer (i5 or i7)
- OS Linux 64-bits (Windows 10 compatible)
- At least 16GB RAM
- Display resolution recommended 1920x1080
Outline
Architecture Overview for Existing Xilinx Users
Versal ACAPs Compared to Zynq UltraScale+ Devices
NoC Introduction and Concepts
NoC Architecture
Design Tool Flow Overview
NoC DDR Memory Controller
NoC Performance Tuning
System Design Migration
Teaching Methods
- Classroom training:
- Face to face
- Presentation by video projector
- Provision of PDF course materials
- Virtual training:
- Onlive training
- Presentation by Webex
- Provision of PDF course materials
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
- Expert SoC & MPSoC XILINX - Language C/C++ - System Design
- Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
- Expert ACAP XILINX – AI Engines – Heteregenous System Architect
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Concerned public
- Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices