Accelerating Applications with the Vitis Unified Environment Software

(ref.AI_ACCEL)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Describe how the FPGA architecture lends itself to parallel computing
    • Explain how the Vitis unified software environment helps software developers to focus on applications
    • Describe the Vitis (OpenCL API) execution model
    • Analyze the OpenCL API memory model
    • Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard
    • Apply host code optimization and kernel optimization techniques
    • Move data efficiently between kernel and global memory
    • Profile the design using the Vitis analyzer tool

Partners

xilinx atp

Prerequisites

  • Basic knowledge of Xilinx FPGA architecture
  • Comfort with the C/C++ programming language
  • Software development flow

Configurations

  • Software Configuration :
    • Vitis unified software platform 2019.2
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS 64-bits (Ubuntu, RedHat, Centos)
    • At least 16GB RAM
    • Recommended display resolution 1920x1080

Outline

Day 1

Introduction to the Vitis Unified Software Platform

Vitis IDE Tool Overview

Vitis Command Line Flow

Introduction to Hardware Acceleration

Alveo Data Center Accelerator Cards Overview

Alveo Accelerator Card Ecosystem Partner Solutions Overview

Getting Started with Alveo Data Center Accelerator Cards

Introduction to the Nimbix Cloud

Vitis Execution Model and XRT

Synchronization

Day 2

Introduction to NDRanges

Working with NDRanges

Profiling

Debugging

Introduction to C/C++ based Kernels

Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators

Optimization Methodology

C/C++ based Kernel Optimization

Host Code Optimization

Optimizing the Performance of the Design

Vitis Accelerated Libraries

Teaching Methods

  • Classroom training:
    • Face to face
    • Presentation by video projector
    • Provision of paper-based course materials
  • Virtual training:
    • Onlive training
    • Presentation by Webex
    • Provision of PDF course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA/SoC/MPSoC/RFSoC/ACAP XILINX - Languages VHDL/Verilog - DSP - Design RTL - Embedded C

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Anyone who needs to accelerate their software applications using FPGAs, SoCs (such as Zynq®-7000 SoCs, Zynq UltraScale+™ MPSoCs), and Versal™ ACAPs