Accelerating Applications with the Vitis Unified Environment Software
(ref.AI_ACCEL)
3 days - 21 hours
Objectives
- After completing this training, you will have the necessary skills to:
- 1 - Explain how the Vitis unified software environment helps software developers
- 2 - Describe how the FPGA architecture lends itself to parallel computing, as well as the ALVEO boards
- 3 - Describe the Vitis execution model (OpenCL API)
- 4 - Profile the design using the Vitis analysis tool
- 5 - Create kernels from C, C++ or RTL IP using the RTL kernel creation wizard
- 6 - Apply host code and kernel optimization techniques
- 7 - Describe existing libraries and create an extensible platform
Prerequisites
- Basic knowledge of Xilinx FPGA architecture
- Comfort with the C/C++ programming language
- Software development flow
Concerned public
- Technicians and Engineers in Digital Electronics
- All our training courses are given at a distance and are accessible to people with reduced mobility.
- Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability.
Notes
- Release date: 20/12/2021
Chapters
Objective 1
- Introduction to the Vitis Unified Software Platform {Lecture}
- Vitis IDE Tool Overview {Lecture, Labs}
- Vitis Command Line Flow {Lecture, Labs}
Objective 2
- Introduction to Hardware Acceleration {Lecture}
- Alveo Data Center Accelerator Cards Overview {Lecture}
- Getting Started with Alveo Data Center Accelerator Cards {Lecture}
Objective 3
- Vitis Execution Model and XRT {Lecture, Labs}
- Synchronization {Lecture, Lab}
- NDRanges {Lecture}
Objective 4
- Profiling {Lecture}
- Debugging {Lecture}
Objective 5
- Introduction to C/C++ based Kernels {Lecture, Lab}
Objective 5
- Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab}
Objective 6
- Optimization Methodology {Lecture}
- C/C++ based Kernel Optimization {Lecture}
- Host Code Optimization {Lecture}
- Optimizing the Performance of the Design {Lecture, Lab}
Objective 7
- Vitis Accelerated Libraries {Lecture}
- Creating a Vitis Embedded Acceleration Platform (Edge) {Lecture}
Teaching Methods
- Inter-company online training :
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
- Expert SoC & MPSoC XILINX - Language C/C++ - System Design
- Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
- Expert ACAP XILINX – AI Engines – Heteregenous System Architect
PC Recommended
- Software Configuration :
- Hardware configuration:
- Recent computer (i5 or i7)
- OS Linux 64-bits
- At least 16GB RAM
- Display resolution recommended 1920x1080