Vivado™ High Level Synthesis

(ref.D_HLS)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Enhance productivity using the Vivado HLS tool
    • Describe the high-level synthesis flow
    • Use the Vivado HLS tool for a first project
    • Identify the importance of the testbench
    • Use directives to improve performance and area and select RTL interfaces
    • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
    • Perform system-level integration of IP generated by the Vivado HLS tool
    • Describe how to use OpenCV functions in the Vivado HLS tool

Partners

xilinx atp

Prerequisites

  • C, C++ or System-C Knowledge
  • Basic Digital Design Concept

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2018.3
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Day 1

Introduction to High-Level Synthesis {Lecture}

Basics of the Vivado HLS Tool {Lecture, Lab}

Design Exploration with Directives {Lecture}

Vivado HLS Tool Command Line Interface {Lecture, Lab}

Introduction to HLS UltraFast Design Methodology {Lecture}

Introduction to I/O Interfaces {Lecture}

Block-Level Protocols {Lecture, Lab}

Port-Level Protocols {Lecture, Lab}

Port-Level Protocols: AXI4 Interfaces {Lecture}

Port-Level Protocols: Memory Interfaces {Lecture, Lab}

Port-Level Protocols: Bus Protocol {Lecture}

Pipeline for Performance: PIPELINE {Lecture, Lab}

Day 2

Pipeline for Performance: DATAFLOW {Lecture, Lab}

Optimizing Structures for Performance {Lecture, Lab}

Data Pack and Data Dependencies {Lecture}

Vivado HLS Tool Default Behavior - Latency {Lecture}

Reduce Latency {Lecture}

Improving Area {Lecture, Lab}

Introduction to HLx Design Flow {Lecture, Lab}

HLS vs. SDSoC Development Environment Flow {Lecture}

Vivado HLS Tool: C Code {Lecture, Lab}

Hardware Modeling {Lecture}

OpenCV Libraries {Lecture}

Pointers {Lecture}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics