Essential DSP implementation techniques for Xilinx™ FPGAs

(ref.D_ESS)

2 days - 14 hours

Objectives

  • Describe the advantages of using FPGAs over traditional processors for DSP designs
  • Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
  • Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
  • Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
  • Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
  • Explain the algorithms for video and imaging systems and their implementations in FPGAs

Partners

xilinx atp

Prerequisites

  • Fundamental understanding of digital signal processing theory and an appreciation of the principles of the following :
    • Sample rates
    • FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filters
    • Oscillators and Mixers
    • FFT (Fast Fourier Transform) algorithm

Configurations

  • No computer is necessary. Only a pencil, eraser and calculator are necessary.

Outline

Back to Basic

  • Traditional DSP vs. FPGA
  • Digital Signal Processing: What, Why, and Where
  • Signed Binary Number Refresher
  • Signed Number Arithmetic
  • Quantization, Saturation, Truncation, and Rounding
  • Latency vs. Throughput

FPGA Architecture

  • 7 Series Families Overview
  • CLB Structure
  • DSP48E1
  • Block RAM Memory Resources

FPGA Math

  • Addition and Subtraction
  • Accumulation
  • Multiplication
  • IP Support and Inference
  • Lab

Shift Registers, RAM and Applications

  • SRL32E
  • Distributed Memory
  • Block Memory
  • Lab

The FIR Filter

  • Overview
  • MAC Engine FIR
  • Semi Parallel FIR
  • Full Parallel FIR
  • Distributed Arithmetic FIR
  • Inference and IP
  • Lab

Advanced Filter Techniques

  • Overview
  • Multiple-Channel Filter
  • Halfband and Interpolated Filters
  • Multiple-Rate Filter: Interpolation Theory
  • Multiple-Rate Filter: Decimation Theory
  • Multiple-Channel, Multiple-Rate Filter
  • Other Functions and Filters
  • Lab

The Fast Fourier Transform

  • Overview
  • FFT Design
  • FFT Core
  • Lab

Video and Imaging

  • Introduction
  • Datapath vs. Post Process
  • Video Processing Techniques
  • Image Processing

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics