VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design

(ref.L_VHDL)

5 days - 35 hours

Objectives

  • Understand the architecture of a Series-7 FPGA
  • Understand the multiple possibilities offered by the VHDL language and understand the concepts of logic synthesis
  • Know the writing styles and their impact on the quality of the synthesis results
  • Know the performance that can be expected from Xilinx FPGAs and the implementation constraints
  • Handle development tools and implementation reports
  • Understand the multiple simulation possibilities offered by the VHDL language and build efficient testbenches

Prerequisites

  • This training is intended to electronic engineers who already have a good knowledge in designing digital electronic circuits, who are willing to acquire a strong designing methodology, and to take the best of VHDL language and the associated synthesis and simulation tools for designing Xilinx FPGA.

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • For other people, in order to find a training or a job adapted to your handicap, you can go on the site of the AGEFIPH https://www.agefiph.fr/

Notes

  • Release date: 13/12/2021

Chapters

Day 1

7-Series FPGA architecture

  • General structure
  • CLB and slices notion
  • Dedicated RAM blocks and use modes
  • Dedicated multipliers and DSP48 blocks
  • In/Out blocks
  • Clocks distribution, MMCMs and PLLs
  • Configuration

Day 2

Writing rules of VHDL code in logical synthesis

  • Notion of entity / architecture
  • Concurrent and sequential instructions
  • Predefined types and objects
  • Predefined operators and of use extended by using standardized packages
  • Concurrent instructions : when, with select, for generate

Day 3

Writing rules of VHDL code in logical synthesis (next)

  • Process

Hierarchy management for a better use

  • Organization of design by functional modules
  • Inference and instancing notions
  • Precautions for an evolutionary and / or re-usable code

Day 4

Advanced VHDL language for optimization and code re-use in logical synthesis

  • Notion of variable and example of use
  • Genericity and automatic configuration of re-usable modules
  • Useful predefined attributes in logical synthesis
  • Functions and procedures
  • Definition of packages and libraries

Hardware designing methodology in logical synthesis

  • Synchronous design
  • Static timing analysis
  • Pipeline notion

Implementation and tuning tools

Day 5

Test benches and simulation

  • A few basic rules for the writing of an efficient testbench
  • VHDL instructions specific to simulation
  • Writing components models intended to make the simulation more realistic
  • Use of existing models and simulation packages
  • Writing and reading of ASCII files
  • Generating information messages

Teaching Methods

  • Inter-company training :
    • Online training
    • Presentation by Webex
    • Provision of course material in PDF format

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

PC Recommended

  • Software Configuration :
    • WebEx Cisco
    • RealVNC Viewer
    • Vivado Design Suite 2020.2
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080

Partner

xilinx atp