VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design

(ref.L_VHDL)

5 days - 35 hours

Objectives

  • After completing this training, you will have the skills to:
    • 1 - Understand the architecture of a Series-7 FPGA
    • 2 - Understand the multiple possibilities offered by the VHDL language and understand the concepts of logic synthesis
    • 3 - Know the writing styles and their impact on the quality of the synthesis results
    • 4 - Handle development tools and implementation reports
    • 5 - Understand the multiple simulation possibilities offered by the VHDL language and build efficient testbenches

Prerequisites

  • This training is intended to electronic engineers who already have a good knowledge in designing digital electronic circuits, who are willing to acquire a strong designing methodology, and to take the best of VHDL language and the associated synthesis and simulation tools for designing Xilinx FPGA.

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability.
              • agefiph

Notes

  • Release date: 13/12/2021

Chapters

Day 1

Objective 1

  • CLB and slices notion
  • Dedicated RAM blocks and use modes
  • Dedicated multipliers and DSP48 blocks
  • In/Out blocks
  • Clocks distribution, MMCMs and PLLs
  • Configuration

Day 2

Objective 2

  • Notion of entity / architecture
  • Concurrent and sequential instructions
  • Predefined types and objects
  • Predefined operators and of use extended by using standardized packages
  • Concurrent instructions : when, with select, for generate

Day 3

Objective 2

  • Process
  • Organization of design by functional modules
  • Inference and instancing notions
  • Precautions for an evolutionary and / or re-usable code

Day 4

Objective 3

  • Notion of variable and example of use
  • Genericity and automatic configuration of re-usable modules
  • Useful predefined attributes in logical synthesis
  • Functions and procedures
  • Definition of packages and libraries

Objective 4

  • Synchronous design
  • Static timing analysis
  • Implementation and tuning tools

Day 5

Objective 5

  • VHDL instructions specific to simulation
  • Writing components models intended to make the simulation more realistic
  • Use of existing models and simulation packages
  • Writing and reading of ASCII files
  • Generating information messages

Teaching Methods

  • Inter-company online training :
    • Presentation by Webex by Cisco
              • Webex de Cisco
    • Provision of course material in PDF format
    • Labs on Cloud PC by RealVNC
              • REALVNC

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

PC Recommended

Partner

xilinx atp