VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design
(ref.L_VHDL)
5 days - 35 hours
Objectives
- Understand the 7-Series FPGA architecture
- Comprehend the various possibilities offered by VHDL language
- Understand the logical synthesis notions
- Know the different writing style and their impact on the quality of synthesis results
- Know the performance that can be expected from Xilinx FPGA
- Learn how to configure compilation options and implementation constraints
- Manipulate the debug tools and implementation reports
Partners
Prerequisites
- This training is intended to electronic engineers who already have a good knowledge in designing digital electronic circuits, who are willing to acquire a strong designing methodology, and to take the best of VHDL language and the associated synthesis and simulation tools for designing Xilinx FPGA.
Configurations
- Software Configuration :
- Xilinx Vivado™ Design Edition 2018.1
- Hardware configuration:
- Recent computer (i5 or i7)
- Windows 7 64b
- At least 8GB RAM
- Minimum display resolution 1024 x 768, recommended 1920x1080
Outline
7-Series FPGA architecture
- General structure
- CLB and slices notion
- Dedicated RAM blocks and use modes
- Dedicated multipliers and DSP48 blocks
- In/Out blocks
- Clocks distribution, MMCMs and PLLs
- Configuration
Writing rules of VHDL code in logical synthesis
- Notion of entity / architecture
- Concurrent and sequential instructions
- Predefined types and objects
- Predefined operators and of use extended by using standardized packages
- Concurrent instructions : when, with select, for generate
- Practical labs
Writing rules of VHDL code in logical synthesis (next)
- Process
- Importance of the sensitivity list
- Sequential instructions : if, case, loop
- Use of variables
- A few tricks to avoid
- Potential interpretation incoherencies between the logical synthesis and the simulation : how to avoid it
Hierarchy management for a better use
- Organization of design by functional modules : what routing to choose ?
- Inference and instancing notions
- When is it important to instantiate primitives or macros ?
- Precautions for an evolutionary and / or re-usable code
- Importance of module’s name selection and of the nets to facilitate the physical implementation, the simulation and the tuning
- Does the hierarchy have to be preserved during the logical synthesis ?
- Practical labs
Advanced VHDL language for optimization and code re-use in logical synthesis
- Notion of variable and example of use
- Genericity and automatic configuration of re-usable modules
- Useful predefined attributes in logical synthesis
- Functions and procedures
- Definition of packages and libraries
- Practical labs
Hardware designing methodology in logical synthesis
- Asynchronous conception and classic tricks
- Metastability and hazards of functioning
- Limits of functional simulation and timing on asynchronous designs : how to get over them?
- Asynchronous event management
- Random
- Data streams
- Synchronous design
- Static timing analysis : how to use it?
- Optimization of performance irrespective of the target
- Pipeline notion
- Practical labs
Implementation and tuning tools
- Implementation flow and bitstream generation
- Reports Analysis
- Main implementation options
- Implementation results analysis tools
Test benches and simulation
- A few basic rules for the writing of an efficient testbench
- VHDL instructions specific to simulation
- Wait and its various forms
- Loop
- Assertions
- Data types
- Others
- Writing components models intended to make the simulation more realistic
- Use of existing models and simulation packages
- Practical labs
- Writing and reading of ASCII files
- Allocation of a data flow from a file
- Storage of the simulation results in a file
- Command interpreter
- Generating information messages
- Practical labs
Teaching Methods
- Face to face
- Presentation by video projector
- Provision of paper-based course materials
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL - DSP - Design RTL
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Concerned public
- Technicians and Engineers in Digital Electronics