Advanced use of the Vivado Design Suite

(ref.F_VADV)

3 days - 21 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Employ good alternative design practices to improve design reliability
    • Define a properly constrained design
    • Increase performance by utilizing FPGA design techniques
    • Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
    • Analyze a timing report to identify how to center the clock in the data eye
    • Utilize floorplanning techniques to improve design performance
    • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
    • Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
    • Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
    • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Partners

xilinx atp

Prerequisites

  • Designing FPGAs Using the Vivado Design Suite
  • Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and UltraFast Design Methodology
  • Intermediate HDL knowledge (VHDL or Verilog)
  • Solid digital design background

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2018.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Vivado Design Suite Non-Project Mode {Lecture}

Scripting in Vivado Design Suite Non-Project Mode {Lecture, Lab}

Revision Control Systems in the Vivado Design Suite {Lecture, Lab}

UltraFast Design Methodology: Design Closure {Lecture}

Timing Simulation {Lecture, Lab}

Synchronization Circuits {Lecture, Lab}

Report Clock Interaction {Lecture}

Report Datasheet {Lecture}

I/O Timing Scenarios {Lecture}

Source-Synchronous I/O Timing {Lecture, Lab}

System-Synchronous I/O Timing {Lecture}

Timing Constraints Priority {Lecture}

Case Analysis {Lecture}

UltraFast Design Methodology: Advance Techniques {Lecture}

Hierarchical Design {Lecture}

Managing Remote IP {Lecture, Lab}

Introduction to the Xilinx Tcl Store {Lecture}

Manipulating Design Properties Using Tcl {Lecture, Lab}

Introduction to Floorplanning {Lecture}

Design Analysis and Floorplanning {Lecture, Lab}

Incremental Compile Flow {Lecture, Lab}

Physical Optimization {Lecture, Lab}

Vivado Design Suite ECO Flow {Lecture, Lab}

Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}

Power Management Techniques {Lecture}

Daisy Chains and Gangs in Configuration {Lecture}

Bitstream Security {Lecture, Lab}

Vivado Design Suite Debug Methodology {Lecture}

Debug Flow in an IP Integrator Block Design {Lecture, Lab}

JTAG to AXI Master Core {Lecture}

Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}

Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab}

Trigger and Debug at Device Startup {Lecture}

Debugging the Design Using Tcl Commands {Lecture, Lab}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics