Designing an Integrated PCI Express System


2 days - 14 hours


  • After completing this comprehensive training, you will have the necessary skills to:
    • Construct a basic PCIe system by:
      • Selecting the appropriate core for your application
      • Specifying requirements of an endpoint application
      • Connecting this endpoint with the core
      • Utilizing FPGA resources to support the core
      • Simulating the design
    • Identify the advanced capabilities of the PCIe specification protocol and feature set


xilinx atp


  • Experience with PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Some experience with Xilinx implementation tools
  • Some experience with a simulation tool, preferably the Vivado® simulator
  • Moderate digital design experience


  • Software Configuration :
    • Vivado Design Suite 2020.2
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080


Course Introduction

Xilinx PCI Express Solutions

Connecting Logic to the Core

PCIe Core Customization

Lab 1: Constructing the PCIe Core

Packet Formatting Details

Simulating a PCIe System Design

Lab 2: Simulating the PCIe Core

Endpoint Application Considerations

PCI Express in Embedded Systems

Lab 3: Using the PCI Express Core in IP Integrator

Application Focus: DMA

Lab 4: Exploring Xilinx DMA

Design Implementation and PCIe Configuration

Lab 5: Implementing the PCIe Design

Root Port Applications

Debugging and Compliance

Lab 6: Debugging the PCIe Design

Interrupts and Error Management

Teaching Methods

  • Classroom training:
    • Face to face
    • Presentation by video projector
    • Provision of PDF course materials
  • Virtual training:
    • Onlive training
    • Presentation by Webex
    • Provision of PDF course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning