Designing with the Zynq UltraScale+ RFSoC

(ref.C_RFSOC)

3 days - 21 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Describing the RFSoC family in general
    • Identifying applications for the RF Data Converter and SD-FEC blocks
    • Configuring, simulating, and implementing the blocks
    • Verifying the RF Data Converter on real hardware

Prerequisites

  • Understanding of the Zynq-MPSoC architecture
  • Basic familiarity with data converter terms and principles
  • Basic familiarity with forward error correction terms and principles

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • For other people, in order to find a training or a job adapted to your handicap, you can go on the site of the AGEFIPH https://www.agefiph.fr/

Notes

  • Release date: 20/12/2021

Chapters

Day 1

Zynq UltraScale+ RFSoC Overview {Lecture, Demo}

RF-ADC Hardware {Lecture, Demo, Lab}

Day 2

RF-DAC Hardware {Lecture, Demo, Lab}

RFSoC Hardware {Lecture, Demo}

Data Converter Design {Lecture, Demo, Lab}

Day 3

Practice on ZCU111 {Lecture, Demo, Lab}

Soft-Decision FEC Hardware {Lecture, Demo, Lab}

Teaching Methods

  • Inter-company training :
    • Online training
    • Presentation by Webex
    • Provision of course material in PDF format

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

PC Recommended

  • Software Configuration :
    • WebEx Cisco
    • RealVNC Viewer
    • Vitis Unified Software Platform 2021.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080
    • Zynq UltraScale+ RFSoC ZCU111 board (will be lent)

Partner

xilinx atp