Designing with the Versal ACAP: Architecture and Methodology and NoC
(ref.ACAP_ARC)
4 days - 28 hours
Objectives
- After completing this comprehensive training, you will have the necessary skills to:
- Describe the Versal ACAP architecture at a high level
- Describe the various engines in the Versal ACP device
- Use the various blocks from the Versal architecture to create complex systems
- Perform system-level simulation and debugging
- Identify and apply different design methodologies
- Identify the major network on chip components in the Versal ACAP
- Include the necessary components to access the NoC from the PL
- Configure connection QoS for efficient data movement
Partners
Prerequisites
- Comfort with the C/C++ programming language
- Vitis™ IDE software development flow
- Hardware development flow with the Vivado® Design Suite
- Basic knowledge of UltraScale™/UltraScale+™ FPGAs and Zynq® UltraScale+ MPSoCs
Configurations
- Software Configuration :
- Vitis unified software platform 2020.2
- PetaLinux 2020.2
- Hardware configuration:
- Recent computer (i5 or i7)
- OS Linux 64-bits
- At least 16GB RAM
- Display resolution recommended 1920x1080
Outline
Architecture Overview
Design Tool Flow
Adaptable Engines (PL)
Processing System
PMC and Boot and Configuration
SelectIO Resources
Clocking Architecture
System Interrupts
Timers, Counters, and RTC
Software Build Flow
Software Stack
DSP Engine
AI Engine
Device Memory
Programming Interfaces
Application Partitioning
PCI Express & CCIX
Serial Transceivers
Power and Thermal Solutions
Debugging
Security Features
System Simulation
System Design Methodology
NoC Introduction and Concepts
NoC Architecture
Design Tool Flow Overview
NoC DDR Memory Controller
NoC Performance Tuning
System Design Migration
Teaching Methods
- Classroom training:
- Face to face
- Presentation by video projector
- Provision of PDF course materials
- Virtual training:
- Onlive training
- Presentation by Webex
- Provision of PDF course materials
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
- Expert SoC & MPSoC XILINX - Language C/C++ - System Design
- Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
- Expert ACAP XILINX – AI Engines – Heteregenous System Architect
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Concerned public
- Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device