Designing with the Adaptive SoC Versal™ : Architecture and Methodology

(ref.ACAP_ARC)

4 days - 28 hours

Objectives

  • After completing this training, you will have the necessary skills to:
    • 1 - Describe the architecture of Versal at a high level.
    • 2 - Describe the different engines of the Versal device
    • 3 - Use the different blocks of the Versal architecture to create complex systems
    • 4 - Identify the programming interfaces and describe the boot and security functions
    • 5 - Know and build compatible software stacks in the Versal
    • 6 - Perform system level simulation and debugging
    • 7 - Identify the main components of the NoC and configure the QoS in Versal
    • 8 - Describe the debugging facilities, GT links, PCIe block
    • 9 - Identify and apply different design methodologies

Prerequisites

  • Comfort with the C/C++ programming language
  • Vitis™ IDE software development flow
  • Hardware development flow with the Vivado® Design Suite
  • Basic knowledge of UltraScale™/UltraScale+™ FPGAs and Zynq™ UltraScale+ MPSoCs

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability.
              • agefiph

Notes

  • Release date: 25/04/2023

Chapters

Day 1

Objective 1

  • Architecture Overview {Lecture}

Objective 2

  • Processing System {Lecture}
  • Adaptable Engines (PL) {Lecture}
  • DSP Engine {Lecture}
  • AI Engine {Lecture}
  • NoC Introduction and Concepts {Lecture, Lab}
  • Design Tool Flow {Lecture, Lab}

Day 2

Objective 3

  • SelectIO Resources {Lecture}
  • Clocking Architecture {Lecture}
  • Timers, Counters, and RTC {Lecture}
  • System Interrupts {Lecture}
  • Device Memory {Lecture}

Objective 4

  • Programming Interfaces {Lecture}
  • PMC and Boot and Configuration {Lecture, Lab}
  • Security Features {Lecture}

Objective 5

  • Software Stack {Lecture}
  • Software Build Flow {Lecture, Lab}

Day 3

Objective 6

  • Application Partitioning {Lecture}
  • System Simulation {Lecture, Lab}

Objective 7

  • NoC Architecture {Lecture}
  • NoC DDR Memory Controller {Lecture}
  • NoC Performance Tuning {Lecture, Lab}

Objective 8

  • Debugging {Lecture}
  • Fabric Debug {Lecture, Lab}
  • Hard Block Debug {Lecture}

Day 4

Objective 8

  • Serial Transceivers {Lecture}
  • PCI Express & CCIX {Lecture}

Objective 9

  • Comparison with UltraScale Devices {Lecture}
  • System Design Migration {Lecture}
  • Power & Thermal Solutions {Lecture, Lab}
  • System and Solution Planning Methodology {Lecture}
  • Hardware, IP, and Platform Development Methodology {Lecture, Lab}
  • System Integration and Validation Methodology {Lecture}

Teaching Methods

  • Inter-company online training :
    • Presentation by Webex by Cisco
              • Webex de Cisco
    • Provision of course material in PDF format
    • Labs on Cloud PC by RealVNC
              • REALVNC

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Support

  • Authorized Trainer Provider AMD : Engineer Electronics and Telecommunications ENSIL
    • Expert AMD FPGA - Language VHDL/Verilog - RTL Design
    • Expert AMD SoC & MPSoC - Language C/C++ - System Design
    • Expert DSP & AMD RFSoC – HLS - Matlab - Design DSP RF
    • Expert AMD Versal – AI Engines – Heteregenous System Architect

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Partner

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