Workshop : Migrating from UltraScale+ FPGA designs to Versal SoC (French Language)
(ref.W_US2VER)
1 day - 7 hours
Target objectives and skills
- After completing this workshop, you will have the necessary skills to:
- Identify the different functional blocks in the AMD Versal™ adaptive SoC
- Describe the different tool flows for the Versal adaptive SoC
- Implement a basic Versal NoC design
- Apply design migration guidelines for PL-only and PS+PL designs
Concerned public
- Technicians and Engineers in Digital Electronics
- All our training courses are given at a distance and are accessible to people with reduced mobility.
- People with disabilities may have special training needs. Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability. Don't hesitate to to discuss your requirements.
Prerequisites
- Any Xilinx device architecture class
- Familiarity with the Vivado® Design Suite
Course content
Architecture Overview for Existing Users {Lecture}
System Design Migration Approach {Lecture}
Design Tool Flow {Lecture, Demo}
NoC Introduction and Concepts {Lecture, Demo}
Programmable Logic Design Migration Considerations {Lecture, Demo}
Processing System Comparison {Lecture}
Teaching Methods
- Inter-company online training :
- Fast Internet connection, webcam, headset
- Presentation by Webex by Cisco
Recommended computer hardware
- Inter-company online training :
- Recent computer OS Linux or Windows 64-bits
- Fast Internet, webcam, headset
- Software tool WebEx Cisco
Teaching staff
- William Duluc, Electronics and Telecoms Engineer, AMD Expert since 2009 and AMD Trainer since 2017 :
- Expert AMD FPGA - Language VHDL/Verilog - RTL Design
- Expert AMD SoC & MPSoC - Language C/C++ - System Design
- Expert DSP & AMD RFSoC – HLS - Matlab - Design DSP RF
- Expert AMD Versal – AI Engines – Heteregenous System Architect
Certified Partner
Notes
- Release date: 18/11/2025