Microcontrôleurs STR9

(ref.004337A)

4 jours

Objectifs

  • The course details the hardware implementation of the STR91x microcontrollers
  • The boot sequence and the clocking are explained
  • Practical labs on integrated peripherals are based on I/O functions provided by ST
  • The course focuses on the low level programming of the ARM7TDMI core
  • The course provides examples of internal peripheral software drivers

Partenaires

ST Microelectronics

Prérequis

  • A basic understanding of microprocessors and microcontrollers is recommended
  • A basic understanding of digital logic or hardware / ASIC design issues would be useful but not essential
  • A basic understanding of assembler or C programming would be useful but not essential

Configurations

  • Pour les formations sur site, les travaux pratiques peuvent etre effectués sous les environnements suivants :Keil µVision, ou IAR Workbench
  • Pour les formations publiques, les travaux pratiques sont effectués avec IAR Workbench

Contenu

ARM core based architecture

Features of AHB and APB buses

The main three blocks : platform, core and input / output peripherals

Operating modes : user, system, super, IRQ, FIQ, undef and abort

Pipeline, calculation of the CPI

Branch cache

Clarifying the data path

Tightly Coupled Memories

ARM vs Thumb instruction sets, interworking

Stack management

Benefits of condition set capability in ARM state

C-to-Assembly interface

Exception mechanism, handler table

Debug facilities

AHB/APB Bridges, split transactions, error handling

Internal 96 KB SRAM,

Flash memory

Program and erase sequences

VIC Interrupt controller

Wake-up / interrupt unit

System timers : Real Time Clock, Watchdog timer

Low voltage detectors

Clocking

Reset causes

Start-up sequence, fetch of the first instruction

Low power modes

External Memory Interface

I/O Ports

Output compare and input capture capabilities, force compare modes

One pulse mode

Output PWM mode, on-the-fly modification of the duty cycle

Input PWM mode, pulse measurement

Request priority management between the 16 channels

Scatter / gather operation, transfer descriptor chaining

Error management

One-shot or continuous conversion

Analog watchdog with interrupt generation

Tacho counter operating modes

Rotor speed measurement

Dead time generator

I2C protocol basics

Slave mode vs master mode

Support for DMA

SPI protocol basics

Queue mode operation

Transfer sequence

Queue operation mode

Hardware flow control

IrDA mode

Support for DMA

CAN protocol basics

CAN controller organization

Message objects

Filtering of received messages

FIFO mode management

USB protocol basics

Buffer description block, buffer descriptor table

DMA controller used to move data between buffers and EndPoints

Endpoint initialization

802.3 MAC basics

Connection to the PHY : MII bus

Management interface, auto-negotiation

DMA controller operation

Frame filtering

VLAN support

Error management

Notes

  • Les supports de cours seront fournis sur papier à chaque participant pendant la formation