Microcontrôleurs Kinetis

(ref.004872A)

4 jours

Objectifs

  • The course details the hardware implementation of the Freescale Kinetis microcontroller series
  • The boot sequence and the clocking are explained
  • The course explains all parameters that affect the performance of the system in order to easily perform the final tuning
  • A description of all internal peripherals is provided
  • A detailed analysis of the ARM Cortex-M4 is provided

Partenaires

FreescaleARM ATC

Prérequis

  • A basic understanding of microprocessors and microcontrollers is recommended
  • A basic understanding of digital logic or hardware / ASIC design issues would be useful but not essential
  • A basic understanding of assembler or C programming would be useful but not essential

Contenu

ARM core based architecture

Clarifying the internal data paths

AHB Multi-Layer interconnect

Organization of a board based on i.MX28

Memory map

Presentation of the core, architecture and programming model

Floating Point Unit

Icode, Dcode and system buses

Branch prediction mechanism

Thumb-2 instruction set

Access to memory-mapped locations, addressing modes

Conditional execution

Bit-banding

Memory map

C-to-Assembly interface

Exception mechanism

System tick timer

System Control Block

linker parameterizing

Embedded software development with Keil

Debug facilities

The Kinetis product line

Internal architecture

Overview of all the peripherals

Memory map

Clock distribution

Clock gating

Resets: Power On Reset, System resets, Debug resets

Boot sources

Boot options

Boot sequence

Power modes

Entering and exiting power modes

Module operation in low power mode

Power Management Controller

Low-Voltage Detector

Low-Leakage Wake-up Unit

Flash Memory Controller

Flash Memory Module

External Bus Interface (FlexBus)

EzPort

Pin interrupt

Edge & level sensitive

Digital input filter

Pull-up, pull-down, pull-disable modes

Pin multiplexing

Drive strengths

Slew rates

GPIOs

Cyclic Redundancy Check

Memory-Mapped Cryptographic Acceleration Unit

Random Number Generator

Analog-to-Digital Converter

Comparator

Digital-to-Analog Converter

Programmable Delay Block

FlexTimer

Periodic Interrupt Timer

Low Power Timer

Carrier Modulator Transmitter

Real Time Clock

Magic packet detection

CRC-32 check and generation

Dynamic flow control

Address filtering

Statistics indicators

Legacy FEC buffers support

IP Protocol Performance Optimization Features

Automatic host-to-network & network-to-host byte ordering

IEEE 1588 support

USB2.0 Low Speed / Full Speed

Buffer Descriptor Table

CAN

CAN protocol basics

CAN controller organization

Filtering of received messages, acceptance filters

FIFO mode management

Test modes : loop back / silent modes

Configuring the bit timing

Remote frames

Time stamping

SPI

Master/Slave modes

TX/RX FIFOs

Programmable polarity and phase

Programmable frame size

6 chip selects

DMA Support

I2C

Multimaster operation

Automatic master to slave switch

Address recognition

Range slave address support

DMA support

8b/9b frames

Programmable input/output polarity

Idle line wakeup

Address wakeup

Break character detection

Hardware flow control

SIM card protocol

Hardware parity generation & check

DMA support

MMC, SD, SDIO, CE-ATA support

Single block, multi block read & write

Suspend & resume transfers

128x32bits internal FIFOs

DMA support

I2S

Normal mode / network mode

Programmable word length

AC97 support

16 input capacitive touch sensing pins

Automatic detection & periodic scan

MCU wake-up capability

Temperature and supply voltage compensation

16 channels data transfers

Transfer Control Descriptors

Channel activation methods

Priority arbitration

Scatter/gather support

MPU

Memory protection architecture

12 programmable regions

Access rights

Peripheral bridges access support

Notes

  • Les supports de cours seront fournis sur papier à chaque participant pendant la formation