ARM Cortex R4/Cortex R4F - Conception système


4 jours - 28 heures


  • Cette formation traite en détails les particularités des cœurs ARM, aussi bien logiciel que matériel dans le but de facilité la mise en oeuvre de cœurs Cortex-R4.
  • Elle est destiné aux :
    • Ingénieurs logiciel qui veulent non seulement obtenir des détails sur la façon d’écrire un logiciel pour processeur ARM Cortex-R4, mais qui souhaitent également comprendre l’implémentation matériel des cœurs au sein d’un microcontrôleur
    • Ingénieurs matériel qui ont besoin de comprendre comment concevoir des systèmes basés sur ARM Cortex-R4 mais également être capable de comprendre les bases de la programmation logicielle sur ces plates-formes




  • Une compréhension de base des microprocesseurs et microcontrôleurs est utile mais non indispensable
  • Une compréhension de base de la logique numérique est utile mais non indispensable
  • Une compréhension de base de la programmation en assembleur ou en langage C est utile mais non indispensable
  • Des notions sur les cœurs ARM sont utiles mais non indispensables


  • Pour les formations sur site, les travaux pratiques peuvent être effectués sous les environnements suivants : Keil DS-5, Keil µVision, ou IAR Workbench


Block diagram

Highlighting the new features with regard to other ARM cores

ARMv7-R architecture

Operating modes

ARM instruction set

Thumb-2 instruction set

Program Status register


System control coprocessor

Configurable options


General points on syntax

Data processing instructions

Branch and control flow instructions

Memory access instructions

Exception generating instructions

If...then conditional blocks

Stack in operation

Exclusive load and store instructions

Accessing special registers

Coprocessor instructions

Memory barriers and synchronization

Interworking ARM and Thumb states

Demonstration of assembly sequences aimed to understand this new instruction set

Floating point number encoding (normalized, tiny, zero, infinite, NAN)

Overview of VFPv3-D16 architecture

General purpose registers, FPU views of the register bank

Compliance with IEEE754 standard

Exception management

NaN handling

Demonstration of floating point calculations generated from C language

Automatic optimization

Instruction scheduling

Tail-call optimization

Parameter passing

Array and structure access

Loop termination

Inline assembler

Stack usage

Global data layout

Highlighting some optimisations through practical labs, for instance tail-call optimization

ROM/RAM remapping

Exception vector table

Reset handler

Initialization : stack pointers, code and data areas

C library initialization


Linker placement rules

Long branch veneers

C library functionality

Placing the stack and heap

Prefetch unit

Studying how instructions are processed step by step

Instruction cycle timing

Dynamic branch prediction mechanism : global history buffer

Guidelines for optimal performance

Data Processing Unit

Dual issue conditions

Return stack

Instruction Memory Barrier

Prefetch queue flush

PMU related events

Memory types, restriction regarding load / store multiple

Device and normal memory ordering

Memory type access restrictions

Access order

Memory barriers, self-modifying code

Memory protection overview, ARM v7 PMSA

Cortex-R4 MPU and bus faults

Fault status and address registers

Region overview, memory type and access control, sub-regions

Region overlapping

Setting up the MPU

Low Interrupt Latency : abandoning load / store instructions in progress

Configuring the state in which exceptions are handled : endian mode, instruction set

Configuring the FIQ as non-maskable

Primecell VICs

Reducing interrupt latency through automatic vector generation

VIC basic signal timing

Connectivity : daisy-chained VIC

Interrupt priority and masking

Abort exception, fault handling

Determining the cause of the fault through CP15 status registers

Precise vs imprecise faults


Using clock enable to determine the ratio between input clock and operation clock

Reset domains, power-on reset and debug reset

Power control, dynamic power management

Wait For Interrupt architecture

Debugging the processor while powered down

Topology : direct connection, multi-master, multi-layer

PL300 AXI interconnect

Separate address/control and data phases

AXI channels, channel handshake

Support for unaligned data transfers

Transaction ordering, out of order transaction completion

Read and write burst timing diagrams

Atomic transactions

Cache basics : organization, replacement algorithm, write policies

Cache organization

Write with allocate policy

Debugging when caches are active

Parity / ECC protection

Understanding transient cache line load / store : linefill buffers, eviction buffer

Accessing the cache RAM from AXI slave interface

Tightly Coupled Memories, address decoding, enabling on reset

ECC/parity protection

Interleaving BTCM accesses initiated by core and AXI DMA connected to AXI slave interface

Store buffer, merging data

L1 caches software read for debug purposes

PMU related events

AXI master interface, write issuing capability, read issuing capability

AXI transaction identifiers

Controlling an external cache

Restrictions on AXI transfers

Determining the number and type of AXI transactions according to memory attributes and instruction type

AXI transaction splitting

AXI slave interface, write issuing capability, read issuing capability

Enabling or disabling AXI slave accesses

Using chip-select to distinguish A-TCM, B-TCM, I-Cache and D-Cache accesses

Using the AXI slave interface to perform built-in self tests

Understanding the error recovery mechanisms

Exclusive accesses, swap instructions, internal exclusive monitor, requirement of an external exclusive monitor when implementing multiple cores

Second-level address decoding


Read timing diagram

Write timing diagram

APB3.0 new features

Performance monitor, event counting

Related interrupts, event bus

Coresight specification overview

CP14 and memory-mapped registers, utilization of an APB slave interface

APB port access permissions

Embedded core debug

Invasive debug : breakpoints and watchpoints

Vector catch

Debug exception

Debug Communication Channel

External debug interface

Understanding how the Debug unit, the Embedded Trace Macrocell and the Cross-Triggering Interface interact

Debugging systems with energy management capabilities


  • Les supports de cours seront fournis sur papier à chaque participant pendant la formation