Zynq™ All Programmable SoC : Embedded Systems Advanced Hardware Design

(ref.E_HWADV)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Assemble an advanced embedded system
    • Take advantage of the various features of the Zynq All Programmable SoC and Kintex® FPGAs, Cortex™-A9 and MicroBlaze processors, including the AXI interconnect, and the various memory controllers
    • Apply advanced debugging techniques, including the use of the Vivado logic analyzer tool for debugging an embedded system and HDL system simulation of processor-based designs
    • Identify the steps involved in integrating a memory controller into an embedded system using the Cortex-A9 and MicroBlaze processors
    • Integrate an interrupt controller and interrupt handler into an embedded design
    • Design a flash memory-based system and boot load from off-chip flash memory
    • Perform HDL-based system simulation

Partners

xilinx atp

Prerequisites

  • FPGA design and Vivado™ Design Suite experience
  • Zynq™ All Programmable SoC : embedded systems hardware design training (E_HW) or equivalent knowledge
  • Zynq™ All Programmable SoC : system architecture training (E_ZSA) or equivalent knowledge
  • Basic understanding of microprocesseur and FPGA architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2017.3
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Overview of Embedded Hardware Development

Hardware-Software Flow {Lab}

Software Overview

Zynq-7000 All Programmable SoC Architecture Overview {Lab}

MicroBlaze Processor Architecture Overview {Lab}

Zynq UltraScale+ MPSoC Overview {Lab}

Debugging

  • Hardware Introduction
  • Hardware - Marking Nets {Lab}
  • Hardware-Software Co-Debugging (Cross-Triggering) {Lab}

Memory Types

  • Memory Overview
  • Block RAM Controllers
  • Static Memory Controllers
  • DDRx Memory Operation
  • Dynamic Memory Controller (Zynq-7000 Device)

Interrupt Concepts

  • Introduction to Interrupts
  • Interrupts and the Zynq-7000 Device
  • General Interrupt Controller
  • Interrupts and the MicroBlaze Processor
  • AXI Interrupt Controller for the MicroBlaze Processor

AXI Concepts

  • AXI Streaming: Introduction
  • MicroBlaze Processor Streaming Ports
  • AXI Streaming FIFO
  • Connecting AXI IP
  • DMA

Zynq-7000 Device PS-PL Interface

PS Peripherals

  • High-Speed: USB
  • High-Speed: Gigabit Ethernet {Lab}
  • Low-Speed: Overview {Lab}
  • Low-Speed: CAN
  • Low-Speed: I2C
  • Low-Speed: SD/SDIO
  • Low-Speed: SPI
  • Low-Speed: UART

Utility Logic

Sharing PS Resources (Hardware Perspective) {Lab}

Multi-Processor Hardware Architecture

Caching

Processor Caching and SCLR

Accelerator Coherency Port

Booting

  • Flow
  • PL {Lab}
  • Flash Image Generation

QEMU: Introduction

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics