Zynq™ All Programmable SoC : Embedded Systems Hardware Design

(ref.E_HW)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Describe the various tools that encompass a Xilinx embedded design
    • Rapidly architect an embedded system containing a MicroBlaze or Cortex-A9 processor using the Vivado IP integrator and Customization Wizard
    • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
    • Create and integrate an IP-based processing system component in the Vivado Design Suite
    • Design and add a custom AXI interface-based peripheral to the embedded processing system
    • Simulate a custom AXI interface-based peripheral using a bus functional model (BFM)

Partners

xilinx atp

Prerequisites

  • FPGA design and Vivado™ Design Suite experience
  • Zynq™ All Programmable SoC : system architecture training (E_ZSA) or equivalent knowledge
  • Basic understanding of microprocesseur and FPGA architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2017.3
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Embedded UltraFast Design Methodology

Overview of Embedded Hardware Development

Driving the IP Integrator Tool {Lab}

Overview of Embedded Software Development

Driving the SDK Tool {Lab}

AXI: Introduction

AXI: Variations

AXI: Transactions {Lab}

Introduction to Interrupts

Interrupts: Hardware Architecture and Support

AXI: Connecting AXI IP

Using the Create and Import Wizard to Create a New AXI IP {Lab}

AXI: BFM Simulation Using Verification IP {Lab}

MicroBlaze Processor Architecture Overview {Lab}

Zynq-7000 All Programmable SoC Architecture Overview {Lab}

Zynq UltraScale+ MPSoC Architecture Overview {Lab}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics