Vitis™ High Level Synthesis

(ref.D_HLS)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Enhance productivity using the Vitis HLS tool
    • Describe the high-level synthesis flow
    • Use the Vitis HLS tool for a first project
    • Identify the importance of the test bench
    • Use directives to improve performance and area and select RTL interfaces
    • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
    • Perform system-level integration of IP generated by the Vitis HLS tool

Partners

xilinx atp

Prerequisites

  • C or C++ knowledge
  • High-level synthesis for software engineers OR high-level synthesis for hardware engineers

Configurations

  • Software Configuration :
    • Vitis HLS tool 2020.2
    • Vivado Design Suite 2020.2
    • Vitis unified software platform 2020.2
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080

Outline

Introduction to High-Level Synthesis

Vitis HLS Tool Flow

Design Exploration with Directives

Vitis HLS Tool Command Line Interface

Introduction to HLS UltraFast Design Methodology

Introduction to I/O Interfaces

Block-Level I/O Protocols

Port-Level I/O Protocols

Port-Level I/O Protocols: AXI4 Interfaces

Port-Level I/O Protocols: Memory Interfaces

Pipeline for Performance: PIPELINE

Pipeline for Performance: DATAFLOW

Optimizing Structures for Performance

Vitis HLS Tool Default Behavior: Latency

Reducing Latency

Improving Area and Resource Utilization

Migrating to the Vitis HLS Tool

HLS Design Flow – System Integration

Vitis HLS Tool C Libraries: Arbitrary Precision

Hardware Modeling

Using Pointers in the Vitis HLS Tool

Teaching Methods

  • Classroom training:
    • Face to face
    • Presentation by video projector
    • Provision of PDF course materials
  • Virtual training:
    • Onlive training
    • Presentation by Webex
    • Provision of PDF course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Software and hardware engineers looking to utilize high-level synthesis