SDSoC Development Environment and Advanced Methodology
(ref.E_SDSOCv)
2 days - 14 hours
Objectives
- After completing this comprehensive training, you will have the necessary skills to:
- Identify candidate functions for hardware acceleration by using the TCF profiling tool
- Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
- Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
- Use the hardware/software event trace to understand the performance of an application given the workload, hardware/software partitioning, and system design choices
- Improve the memory accesses and data transfer rate between the PS and PL (macro-architecture optimization)
- Apply HLS directives to enhance the performance of hardware functions (micro-architecture optimization)
- Create a C-callable library for IP blocks written in a hardware description language like VHDL or Verilog
- Override tool defaults to improve the performance of individual accelerators and the overall system
- Create a custom platform using the SDSoC Platform Utility (sdspfm)
Partners
Prerequisites
- C or C++ Knowledge
- Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK
- Understanding of Zynq®-7000 architecture (with emphasis on ACP or HP)
Configurations
- Software Configuration :
- Xilinx SDx Environment 2019.1 (last version, no upgrade later)
- Hardware configuration:
- Recent computer (i7 or i9)
- Windows 7 64b
- At least 16GB RAM
- Minimum display resolution 1024 x 768, recommended 1920x1080
Outline
SDSoC Tool Flow
Application Debugging
Application Profiling
Understanding Estimations in the SDSoC Tool
Hardware/Software Event Tracing
C-Callable IP Library
SDSoC Platform Creation
SDSoC Environment Optimization
Memory Access Optimization
Blocking and Non-Blocking Implementations in the SDSoC Tool
Implementing Multiple Accelerators in the SDSoC Tool
Basics of the Vivado HLS Tool
Design Exploration with Directives (Pragmas)
Pipeline for Performance: PIPELINE
Pipeline for Performance: DATAFLOW
Teaching Methods
- Face to face
- Presentation by video projector
- Provision of paper-based course materials
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL - DSP - Design RTL
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Concerned public
- Technicians and Engineers in Digital Electronics