Advanced SDSoC Development Environment and Methodology

(ref.E_ADVSDS)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Improve the memory accesses and data transfer rate between the PS and PL (macro-architecture optimization)
    • Apply HLS directives to enhance the performance of hardware functions (micro-architecture optimization)
    • Create a C-callable library for IP blocks written in a hardware description language like VHDL or Verilog
    • Override tool defaults to improve the performance of individual accelerators and the overall system
    • Create a custom platform using the SDSoC Platform Utility (sdspfm)
    • Describe how the reVISION Stack enables users to quickly develop applications based on machine learning and computer vision with the SDx development environment

Partners

xilinx atp

Prerequisites

  • C or C++ Knowledge
  • Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK
  • Understanding of Zynq®-7000 architecture (with emphasis on ACP or HP)
  • SDSoC Development Environment and Methodology course

Configurations

  • Software Configuration :
    • Xilinx SDx Environment 2017.4
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

SDSoC Environment Optimization

Memory Access Optimization

Blocking and Non-Blocking Implementations in the SDSoC Tool

Implementing Multiple Accelerators in the SDSoC Tool

Basics of the Vivado HLS Tool

Design Exploration with Directives (Pragmas)

Pipeline for Performance: PIPELINE

Pipeline for Performance: DATAFLOW

Optimizing Structures for Performance

C-Callable IP Library

SDSoC Platform Creation

Optimizing the Design

reVISION Stack

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics