Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment

(ref.E_OCLSDA)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Describe how the FPGA architecture lends itself to parallel computing
    • Explain how the SDx development environment helps software developers to focus on applications
    • Examine the OpenCL API execution model
    • Analyze the OpenCL API memory model
    • Create kernels from C, C++, OpenCL, or RTL IP (using the RTL Kernel Wizard)
    • Apply host code optimization and kernel optimization techniques
    • Move data efficiently between kernel and global memory
    • Profile and debug OpenCL API code using the SDAccel development environment

Partners

xilinx atp

Prerequisites

  • Basic knowledge of Xilinx FPGA architecture
  • Comfort with the C/C++ programming language

Configurations

  • Software Configuration :
    • Xilinx SDx Environment 2018.3 (license required)
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Linux, 64-bit:
      • Ubuntu 16.04.5 LTS, 18.04.1 LTS
      • CentOS 7.4, 7.5, 7.6
      • RHEL 7.4, 7.5, 7.6
    • At least 16GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Introduction to the SDAccel Environment and OpenCL Framework {Lecture}

SDx Tools Overview {Lecture, Lab}

Makefile Flow {Lecture, Lab}

Introduction to FPGAs {Lecture}

Alveo Product Overview {Lecture}

Alveo Partner Ecosystem Solutions Overview {Lecture}

Introduction to Nimbix Cloud {Lecture}

OpenCL Framework Fundamentals 1 {Lecture}

OpenCL Framework Fundamentals 2 {Lecture, Lab}

Synchronization {Lecture, Lab}

Introduction to NDRanges {Lecture}

Working with NDRanges {Lecture, Lab}

Profiling {Lecture}

Debugging {Lecture}

C-Based Kernels {Lecture}

C-Based Kernel Optimization {Lecture}

Optimization Methodologies {Lecture}

Memory Transfer Optimization Techniques {Lecture}

Kernel Optimization Techniques {Lecture, Lab}

Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators {Lecture, Lab}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics