Vivado™ Design Suite : Static Timing Analysis and Xilinx Design Constraints


3 days - 21 hours


  • This course offers detailed training on the Vivado™ software tool flow, Xilinx design constraints (XDC), static timing analysis (STA), good FPGA design practices, and how to use Vivado™ unified database.
    • Use good alternative design practices to improve design reliability
    • Increase performance by utilizing FPGA design techniques
    • Describe the details of Vivado IDE database objects
    • Identify Tcl commands for interacting with the database
    • Apply complete Xilinx design constraints (XDC), including timing exceptions, false paths, and multi-cycle path constraints
    • Utilize static timing analysis (STA) to analyze timing results
    • Pinpoint design bottlenecks by using appropriate timing reports
    • Apply advanced I/O timing constraints to meet performance goals
    • Describe different synthesis options and how they can improve design performance


xilinx atp


  • Intermediate knowledge in HDL language and a first experience with the Vivado™ Design suite and FPGAs.
  • Knowledge/experience with the basics of the TCL language.


  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2017.3
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080


Design Methodology Summary


FPGA Design Techniques

Accessing the Design Database

  • Lab

Static Timing Analysis and Clocks

  • Lab

Inputs and Outputs

  • Lab : IO Constraints

Timing Exceptions

  • Lab

Synthesis Techniques

FPGA Design Methodology Checklist

FPGA Design Methodology

HDL Coding Techniques

Reset Methodology

  • Lab : Resets
  • Lab : SRL and DSP Inference

Synchronization Circuits and the Clock Interaction Report

Timing Closure

FPGA Design Methodology Case Study

  • Lab

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics