Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and Advanced use of Vivado

(ref.F_STAXDC)

4 days - 28 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Describe the UltraFast™ design methodology checklist
    • Identify key areas to optimize your design to meet your design goals and performance objectives
    • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
    • Build resets into your system for optimum reliability and design speed
    • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
    • Identify timing closure techniques using the Vivado Design Suite
    • Apply complete Xilinx design constraints (XDC), including timing exceptions, false paths, and multi-cycle path constraints
    • Utilize static timing analysis (STA) to analyze timing results
    • Pinpoint design bottlenecks by using appropriate timing reports
    • Apply advanced I/O timing constraints to meet performance goals
    • Utilize floorplanning techniques to improve design performance
    • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode
    • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Partners

xilinx atp

Prerequisites

  • Intermediate knowledge in HDL language and a first experience with the Vivado™ Design suite and FPGAs.
  • Knowledge/experience with the basics of the TCL language.

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2019.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Day 1

Introduction to FPGA Architecture, 3D ICs, SoCs

UltraFast Design Methodology: Board and Device Planning

UltraFast Design Methodology: Design Creation

HDL Coding Techniques

Pipelining

Inference

Vivado Design Suite Flows

Scripting in Vivado Design Suite

Vivado Synthesis and Implementation

Introduction to Vivado Reports

Baselining

Timing Constraints Editor

Timing Summary Report

Day 2

Clocking Resources

Introduction to Clock Constraints

Generated Clocks

Report Clock Networks

Clock Group Constraints

Report Clock Interaction

Setup and Hold Timing Analysis

I/O Constraints and Virtual Clocks

Timing Constraints Wizard

Introduction to Timing Exceptions

Day 3

Synchronous Design Techniques

Synchronization Circuits

Resets

UltraFast Design Methodology: Implementation

UltraFast Design Methodology: Design Closure

Report QoR

Register Duplication

Report Datasheet

I/O Timing Scenarios

System-Synchronous I/O Timing

Source-Synchronous I/O Timing

I/O Logic Resources

Timing Constraints Priority

Case Analysis

Physical Optimization

Day 4

Introduction to Floorplanning

Design Analysis and Floorplanning

Congestion

Incremental Compile Flow

Vivado Design Suite ECO Flow

JTAG to AXI Master Core

Remote Debugging Using the Vivado Logic Analyzer

Trigger and Debug at Device Startup

Trigger Using the Trigger State Machine in the Vivado Logic Analyzer

Revision Control Systems in the Vivado Design

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics