Static Timing Analysis (STA), Xilinx Design Constraints (XDC) and UltraFast Design Methodology


3 days - 21 hours


  • After completing this comprehensive training, you will have the necessary skills to:
    • Describe the UltraFast™ design methodology checklist
    • Identify key areas to optimize your design to meet your design goals and performance objectives
    • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
    • Build resets into your system for optimum reliability and design speed
    • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
    • Identify timing closure techniques using the Vivado Design Suite
    • Apply complete Xilinx design constraints (XDC), including timing exceptions, false paths, and multi-cycle path constraints
    • Utilize static timing analysis (STA) to analyze timing results
    • Pinpoint design bottlenecks by using appropriate timing reports
    • Apply advanced I/O timing constraints to meet performance goals


xilinx atp


  • Intermediate knowledge in HDL language and a first experience with the Vivado™ Design suite and FPGAs.
  • Knowledge/experience with the basics of the TCL language.


  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2018.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080


Introduction to FPGA Architecture, 3D IC, SoC {Lecture}

UltraFast Design Methodology: Planning {Lecture}

HDL Coding Techniques {Lecture}

Introduction to Vivado Design Flows {Lecture}

Vivado Design Suite Project Mode {Lectures, Lab}

Synthesis and Implementation {Lecture, Lab}

Introduction to Vivado Reports {Lecture}

Introduction to Clock Constraints {Lecture, Lab}

Generated Clocks {Lecture}

Report Clock Networks {Lecture}

Timing Constraints Editor {Lecture}

Clock Group Constraints {Lecture}

Report Clock Interaction {Lecture}

Setup and Hold Timing Analysis {Lecture}

Timing Summary Report {Lecture}

I/O Constraints and Virtual Clocks {Lecture, Lab}

Timing Constraints Wizard {Lecture, Lab}

Introduction to Timing Exceptions {Lecture, Lab}

Synchronous Design Techniques {Lecture}

Synchronization Circuits {Lecture, Lab}

Resets {Lecture, Lab}

UltraFast Design Methodology: Design Closure {Lecture}

Report Datasheet {Lecture}

I/O Timing Scenarios {Lecture}

Source-Synchronous I/O Timing {Lecture, Lab}

System-Synchronous I/O Timing {Lecture}

Timing Constraints Priority {Lecture}

Case Analysis {Lecture}

Physical Optimization {Lecture, Lab}

Introduction to Floorplanning {Lecture}

Design Analysis and Floorplanning {Lecture, Lab}

Congestion {Lecture}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics