Designing FPGAs Using the Vivado Design Suite


3 days - 21 hours


  • After completing this comprehensive training, you will have the necessary skills to:
    • Use the New Project Wizard to create a new Vivado IDE project
    • Describe the supported design flows of the Vivado IDE
    • Generate a DRC report to detect and fix design issues early in the flow
    • Use the Vivado IDE I/O Planning layout to perform pin assignments
    • Synthesize and implement the HDL design
    • Apply clock and I/O timing constraints and perform timing analysis
    • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
    • Describe and use the clock resources in a design
    • Use the Vivado IP integrator to create a block design
    • Create and package your own IP and add to the Vivado IP catalog to reuse
    • Describe how an FPGA is configured
    • Use the Vivado logic analyzer and debug flows to debug a design
    • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer


xilinx atp


  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge


  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2018.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080


Introduction to FPGA Architecture, 3D IC, SoC {Lecture}

UltraFast Design Methodology: Planning {Lecture}

HDL Coding Techniques {Lecture}

Introduction to Vivado Design Flows {Lecture}

Vivado Design Suite Project Mode {Lectures, Lab}

Synthesis and Implementation {Lecture, Lab}

Basic Design Analysis in the Vivado IDE {Lab}

Vivado Design Rule Checks {Lab}

Vivado Design Suite I/O Pin Planning {Lecture, Lab}

Vivado IP Flow {Lecture, Lab}

Timing Constraints Wizard {Lecture, Lab}

Timing Constraints Editor {Lecture}

Introduction to Vivado Reports {Lecture}

UltraFast Design Methodology: Design Creation and Analysis {Lecture}

Synchronous Design Techniques {Lecture}

Setup and Hold Timing Analysis {Lecture}

Timing Report {Lecture}

Clocking Resources {Lecture, Lab}

Introduction to Clock Constraints {Lecture, Lab}

I/O Logic Resources {Lecture}

I/O Constraints and Virtual Clocks {Lecture, Lab}

Creating and Packaging Custom IP {Lecture, Lab}

Using an IP Container {Lecture}

Designing with IP Integrator {Lecture, Lab}Timing Summary Report {Lecture}

Power Analysis and Optimization Using the Vivado Design Suite {Lecture, Lab}

Scripting in Vivado Design Suite Project Mode {Lecture, Lab}

Introduction to FPGA Configuration {Lecture}

Configuration Process {Lecture}

Introduction to the Vivado Logic Analyzer {Lecture}

Introduction to Triggering {Lecture}

Debug Cores {Lecture}

HDL Instantiation Debug Probing Flow {Lecture, Lab}

Netlist Insertion Debug Probing Flow {Lecture, Lab}

Sampling and Capturing Data in Multiple Clock Domains {Lecture, Lab}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics