Designing FPGAs Using the Vivado Design Suite

(ref.F_VBASE)

4 days - 28 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Use the New Project Wizard to create a new Vivado IDE project
    • Describe the supported design flows of the Vivado IDE
    • Generate a DRC report to detect and fix design issues early in the flow
    • Use the Vivado IDE I/O Planning layout to perform pin assignments
    • Synthesize and implement the HDL design
    • Apply clock and I/O timing constraints and perform timing analysis
    • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
    • Describe and use the clock resources in a design
    • Use the Vivado IP integrator to create a block design
    • Create and package your own IP and add to the Vivado IP catalog to reuse
    • Describe how an FPGA is configured
    • Use the Vivado logic analyzer and debug flows to debug a design
    • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer

Partners

xilinx atp

Prerequisites

  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge

Configurations

  • Software Configuration :
    • Vivado Design Suite 2019.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080

Outline

Introduction to Vivado Design Flows

Introduction to FPGA Architecture, 3D IC, SoC

UltraFast Design Methodology: Planning

Vivado Design Suite I/O Pin Planning

Vivado Design Suite Project Mode

Scripting in Vivado Design Suite Project Mode

UltraFast Design Methodology: Design Creation and Analysis

HDL Coding Techniques

Inference

Simulation

Synthesis and Implementation

Introduction to Vivado Reports

Vivado IP Flow

Creating and Packaging Custom IP

Using an IP Container

Designing with IP Integrator

Power Analysis and Optimization Using the Vivado Design Suite

Baselining

Timing Constraints Editor

Timing Summary Report

Clocking Resources

Introduction to Clock Constraints

Generated Clocks

Report Clock Networks

Clock Group Constraints

Report Clock Interaction

Setup and Hold Timing Analysis

I/O Logic Resources

I/O Constraints and Virtual Clocks

Timing Constraints Wizard

Introduction to Timing Exceptions

Synchronous Design Techniques

Synchronization Circuits

Timing Constraints Priority

Introduction to FPGA Configuration

Configuration Process

Configuration Modes

Daisy Chains and Gangs in Configuration

Bitstream Security

Introduction to the Vivado Logic Analyzer

Introduction to Triggering

Debug Cores

HDL Instantiation Debug Probing Flow

Netlist Insertion Debug Probing Flow

Debug Flow in an IP Integrator Block Design

Revision Control Systems in the Vivado Design

Teaching Methods

  • Classroom training:
    • Face to face
    • Presentation by video projector
    • Provision of PDF course materials
  • Virtual training:
    • Onlive training
    • Presentation by Webex
    • Provision of PDF course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics