Partial Reconfiguration

(ref.F_PR)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Build and assemble a Partially Reconfigurable (PR) system
    • Define PR regions and reconfigurable modules with the Vivado™ Design Suite
    • Generate the appropriate full and partial bitstreams for PR design
    • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
    • Implement a PR system using the following techniques
      • Direct JTAG connection
      • Timing constraints and analysis
      • Floorplanning
    • Implement a PR system using the PRC IP
    • Implement a PR system in an embedded environment
    • Debug PR designs

Prerequisites

  • Intermediate knowledge in HDL language and a good experience with the Vivado™ Design suite and FPGAs
  • Vivado™ Design Suite : Static Timing Analysis (STA) and Xilinx Design Constraints (XDC) training (F_STAXDC) or equivalent knowledge

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • For other people, in order to find a training or a job adapted to your handicap, you can go on the site of the AGEFIPH https://www.agefiph.fr/

Notes

  • Release date: 20/12/2021

Chapters

Partial Reconfiguration Methodology

Partial Reconfiguration Tool Flow

Lab 1: Partial Reconfiguration Flow

Lab 2: Floorplanning the PR Design

FPGA Configuration Overview

Partial Reconfiguration Bitstreams

Lab 3: Using the Partial Reconfiguration Controller in a PR Design

Managing Clocks, I/Os, and GTs

Partial Reconfiguration: Managing Timing

Lab 4: Partial Reconfiguration Timing Analysis and Constraints

Partial Reconfiguration in Embedded Systems

Lab 5: Partial Reconfiguration in Embedded Systems

Debugging Partial Reconfiguration Designs

Lab 6: Debugging a Partial Reconfiguration Design

Partial Reconfiguration Design Recommendations

PCIe Core and Partial Reconfiguration

Teaching Methods

  • Inter-company training :
    • Online training
    • Presentation by Webex
    • Provision of course material in PDF format

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
    • Expert SoC & MPSoC XILINX - Language C/C++ - System Design
    • Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
    • Expert ACAP XILINX – AI Engines – Heteregenous System Architect

PC Recommended

  • Software Configuration :
    • WebEx Cisco
    • RealVNC Viewer
    • Vivado Design Suite 2021.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • OS Linux 64-bits (Windows 10 compatible)
    • At least 16GB RAM
    • Display resolution recommended 1920x1080

Partner

xilinx atp