Designing with the Virtex-6 Family

(ref.F_V6)

2 days - 14 hours

Objectives

  • Learn how to effectively use Xilinx Virtex™-6 architectural resources.
    • Understand the CLBs and different type of slices structure.
    • Understand clocks resources (MMCM and also global, horizontal, regional and IO clocks).
    • Design effectively with block RAM and block DSP.
    • Effectively use I/O blocks especially with SERDES blocks.
    • Know the memory controllers
    • Use proper VHDL coding techniques.
    • Discover the integrated hardware resources (Multi-Gigabit Transceivers, PCI-e, MAC Ethernet and System Monitor)

Partners

xilinx atp

Prerequisites

  • Basic knowledge FPGAs architectures.
  • A successful first experience of designing an VHDL or Verilog based FPGA.

Configurations

  • Software Configuration :
    • Xilinx ISE Design Suite 13.1 Logic Edition
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows XP or 7
    • At least 4Go RAM
    • Minimum display resolution 1024 x 768

Outline

Virtex-6 family overview

CLB and Slices architecture

VHDL Coding techniques

  • Lab : CLB resources

Memory Resources

DSP Blocks

  • Lab : DSP resources

I/O Blocks

I/O Blocks (continuation)

  • Lab : I/O Resources

Clocking Resources and management

  • Lab : Clocking Resources

Memory controller

Introduction to dedicated resources (MGT, PCI-e and EMAC)

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics