Designing with the Xilinx™ UltraScale and UltraScale+ Families

(ref.F_US)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Take advantage of the primary UltraScale architecture resources
    • Describe the new CLB capabilities and the impact that they make on your HDL coding style
    • Define the block RAM, FIFO, and DSP resources available
    • Describe the UltraRAM features
    • Properly design for the I/O and SERDES resources
    • Identify the MMCM, PLL, and clock routing resources included
    • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
    • Describe the additional features of the dedicated transceivers
    • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Partners

xilinx atp

Prerequisites

  • Basic knowledge FPGAs architectures
  • A successful first experience of designing an VHDL–based FPGA using Vivado™ Design Suite

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2017.3
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Introduction to the UltraScale Architecture {Lecture}

UltraScale Architecture CLB Resources {Lecture, Lab}

HDL Coding Techniques {Lecture, Lab}

UltraScale Architecture Clocking Resources {Lectures, Lab}

FPGA Design Migration {Lecture, Lab}

Clocking Migration {Lab}

UltraScale Architecture Block RAM Memory Resources {Lecture}

UltraScale Architecture FIFO Memory Resources {Lecture}

UltraRAM Memory {Lecture, Lab}

UltraScale Architecture DSP Resources {Lecture, Lab}

Design Migration Software Recommendations {Lecture}

DDR3 MIG Design Migration {Lab}

DDR4 Design Creation Using MIG {Lab}

UltraScale Architecture I/O Resources Overview {Lecture}

UltraScale Architecture I/O Resources – Component Mode {Lecture, Lab}

UltraScale Architecture I/O Resources – Native Mode {Lecture, Lab}

Design Migration Methodology {Lecture}

10G PCS/PMA and MAC Design Migration {Lab}

UltraScale Architecture Transceivers {Lecture}

UltraScale FPGAs Transceivers Wizard {Lecture, Lab}

Introduction to the UltraScale+ Families {Lecture}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics