Essential DSP implementation techniques for Xilinx™ FPGAs
(ref.D_ESS)
2 days - 14 hours
Objectives
- After completing this training, you will have the necessary skills to:
- 1 - Describe the advantages of using FPGAs over traditional processors for DSP designs, utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
- 2 - Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
- 3 - Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
- 4 - Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
Prerequisites
- Fundamental understanding of digital signal processing theory and an appreciation of the principles of the following :
- Sample rates
- FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filters
- Oscillators and Mixers
- FFT (Fast Fourier Transform) algorithm
Concerned public
- Technicians and Engineers in Digital Electronics
- All our training courses are given at a distance and are accessible to people with reduced mobility.
- Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability.
Notes
- Release date: 20/12/2021
Chapters
Objective 1
- Back to basics {Lecture}
Objective 2
- Architecture of FPGAs {Lecture}
- Mathematics of FPGAs {Lecture, Lab}
Objective 3
- Shift registers, memory and application {Lecture, Lab}
Objective 4
- The FIR filter {Lecture, Lab}
Objective 4
- Advanced filtering techniques {Lecture, Lab}
- The Fast Fourier Transform {Lecture, Lab}
Teaching Methods
- Inter-company online training :
Methods of monitoring and assessment of results
- Attendance sheet
- Evaluation questionnaire
- Evaluation sheet on:
- Technical questionnaire
- Result of the Practical Works
- Validation of Objectives
- Presentation of a certificate with assessment of prior learning
Support
- Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
- Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
- Expert SoC & MPSoC XILINX - Language C/C++ - System Design
- Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
- Expert ACAP XILINX – AI Engines – Heteregenous System Architect
PC Recommended
- Software Configuration :
- WebEx Cisco
- RealVNC Viewer
- Vivado Design Suite 2021.1
- Matlab (or equivalent)
- Hardware configuration:
- Recent computer (i5 or i7)
- OS Linux 64-bits (Windows 10 compatible)
- At least 16GB RAM
- Display resolution recommended 1920x1080