Designing with Xilinx Serial Transceivers


2 days - 14 hours


  • After completing this comprehensive training, you will have the necessary skills to:
    • Describe and utilize the ports and attributes of the serial transceivers in the UltraScale FPGAs
    • Effectively utilize the following features of the gigabit transceivers:
      • 8B/10B and other encoding/decoding, comma detection, clock correction, and channel bonding
      • Pre-emphasis and linear equalization
    • Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
    • Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design
    • Use the IBERT design to verify transceiver links on real hardware


xilinx atp


  • Verilog or VHDL experience (or the Designing with Verilog or the Designing with VHDL course)
  • Familiarity with logic design (state machines and synchronous design)
  • Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful


  • Software Configuration :
    • Xilinx Vivado™ System Edition 2016.3
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080


7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview

7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets

Transceiver Wizard Overview

Lab 1: Transceiver Core Generation

Transceiver Simulation

Lab 2: Transceiver Simulation

PCS Layer General Functionality

PCS Layer Encoding

Lab 3: 64B/66B Encoding

Transceiver Implementation

Lab 4: Transceiver Implementation

PMA Layer Details

PMA Layer Optimization

Lab 5: IBERT Design

Transceiver Test and Debugging

Lab 6: Transceiver Debugging

Transceiver Board Design Considerations

Transceiver Application Examples

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics