MVD TRAINING

Workshop : Getting Started with Xilinx Versal ACAP Platform (French Language) 9h - 17h CET

(ref.A_START)

1 day - 7 hours

Objectives

• In the Event, you will be introduced to the new Xilinx Versal ACAP platform and its building blocks that enable flexible implementation of accelerated systems. Features unique to Versal, such as the AI Engine and Network-on-Chip (NoC) along with the Vitis Unified Software tool flows will be covered. The objective is to let you relate your new applications to Versal and enable you to explore the platform and the tools.

Prerequisites

• Comfort with the C/C++ programming language
• Vitis™ IDE software development flow
• Hardware development flow with the Vivado® Design Suite
• Basic knowledge of UltraScale™/UltraScale+™ FPGAs and Zynq® UltraScale+ MPSoCs

Concerned public

• Technicians and Engineers in Digital Electronics
• All our training courses are given at a distance and are accessible to people with reduced mobility.
• For other people, in order to find a training or a job adapted to your handicap, you can go on the site of the AGEFIPH https://www.agefiph.fr/

Notes

• Release date: 20/12/2021

Chapters

Teaching Methods

• Inter-company training:
• Onlive training
• Presentation by Webex
• Provision of PDF course materials

Support

• Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
• Expert FPGA XILINX - Language VHDL/Verilog - RTL Design
• Expert SoC & MPSoC XILINX - Language C/C++ - System Design
• Expert DSP & RFSoC XILINX – HLS - Matlab - Design DSP RF
• Expert ACAP XILINX – AI Engines – Heteregenous System Architect

PC Recommended

• Software Configuration :
• WebEx Cisco
• Vivado 2021.1
• Hardware configuration:
• Recent computer (i5 or i7)
• OS Linux 64-bits (Windows 10 compatible)
• At least 16GB RAM
• Recommended display resolution 1920x1080

Partner