Zynq UltraScale+™ MPSoC : Hardware Design


1 day - 7 hours


  • This course provides hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.
  • After completing this comprehensive training, you will have the necessary skills to:
    • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
    • List the various power domains and how they are controlled
    • Describe the connectivity between the processing system (PS) and programmable logic (PL)
    • Utilize QEMU to emulate hardware behavior


xilinx atp


  • Understanding of the Zynq-7000 architecture
  • Familiarity with embedded operating systems


  • Software Configuration :
    • Vivado® Design Suite 2018.1 (May require special Zynq UltraScale+ MPSoC family license)
  • Hardware emulation environment :
    • VirtualBox
    • QEMU
    • Ubuntu desktop
    • PetaLinux
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080


Zynq UltraScale+ MPSoC Application Processing Unit {Lecture, Lab}

Zynq UltraScale+ MPSoC Real-Time Processing Unit {Lecture, Lab}

QEMU {Lecture, Lab}

Zynq UltraScale+ MPSoC HW-SW Virtualization {Lecture, Lab}

Zynq UltraScale+ MPSoC Booting {Lecture, Lab}

Zynq UltraScale+ MPSoC System Protection {Lecture}

Zynq UltraScale+ MPSoC Clocks and Resets {Lecture}

Zynq UltraScale+ MPSoC PMU {Lecture, Lab}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials


  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics