Microcontrôleurs STR750F

(ref.004384A)

4 jours

Objectifs

  • The course details the hardware implementation of the STR750F microcontrollers
  • The boot sequence and the clocking are explained
  • Practical labs on integrated peripherals are based on I/O functions provided by ST
  • The course focuses on the low level programming of the ARM7TDMI core
  • The course provides examples of internal peripheral software drivers

Partenaires

ST Microelectronics

Prérequis

  • A basic understanding of microprocessors and microcontrollers is recommended
  • A basic understanding of digital logic or hardware / ASIC design issues would be useful but not essential
  • A basic understanding of assembler or C programming would be useful but not essential

Configurations

  • Pour les formations sur site, les travaux pratiques peuvent etre effectués sous les environnements suivants :Keil µVision, ou IAR Workbench
  • Pour les formations publiques, les travaux pratiques sont effectués avec IAR Workbench

Contenu

ARM core based architecture

APB internal busses

The main three blocks : platform, core and input / output peripherals

Presentation of the core, architecture and programming model

Operating modes : user, system, super, IRQ, FIQ, undef and abort

Pipeline

ALU data path

ARM vs Thumb instruction sets, interworking

Access to memory-mapped locations, addressing modes

Stack management

Branch instructions, implementation of C call and return statements

Benefits of condition set capability in ARM state

C-to-Assembly interface

Exception mechanism, handler table

Debug facilities

APB Bridges, individual peripheral reset control, individual peripheral clock control

Memory organization, linear 4 GB mapping

Internal 16 kB SRAM

Flash memory, bank and sector mapping, burst mode

Program and erase sequences

Interrupt controller

ISR header and footer routines

External interrupts Unit

System timers : Real Time Clock, Watchdog timer

Power supplies, external 3.3V, internal generation of 1.8V, related pins

Low voltage detectors

Clocking

Reset causes

Start-up sequence, fetch of the first instruction

Boot configuration register

Low power modes

External Memory Interface

Description of the programming interface related to the 4 external chip-selects

DMA

Circular Buffer Management

Support for UART, SPI / SSI, Timers and ADC

16-bit timers, block diagram, clock selection and prescalers

Output compare and input capture capabilities, force compare modes

Output PWM mode, on-the-fly modification of the duty cycle

Input PWM mode, pulse measurement

High impedance-analog input configuration

ADC features : 10-bit resolution, 0 to 2.5 V range

Round-robin or single channel mode

Clock timing

The Sinc decimation filter

Gain and offset errors

I2C protocol basics

Slave mode vs master mode

Transmit and receive sequences

SPI protocol basics

Queue mode operation

Transfer sequence

Queue operation mode

Time-out mechanism

LIN capability

SmartCard asynchronous protocol

CAN protocol basics

CAN controller organization

Message objects

Filtering received messages

FIFO mode management

Configuring the bit timing

USB protocol basics

Buffer description block, buffer descriptor table

Double buffer usage to support isochronous and high throughput bulk transfers

Endpoint initialization

Notes

  • Les supports de cours seront fournis sur papier à chaque participant pendant la formation