Microcontrôleurs i.MX31

(ref.004732A)

4 jours

Objectifs

  • The course details the hardware implementation of the i.MX31 microcontroller
  • The boot sequence and the clocking are explained
  • The course explains all parameters that affect the performance of the system in order to easily perform the final tuning
  • A description of all internal peripherals is provided
  • An overview of the ARM1136 core helps to understand issues caused by cache and MMU
  • The course ends with practical labs explaining how to generate a Linux image as well as a Root File System, by using a tool called LTIB [Linux Target Image Builder]

Partenaires

FreescaleARM ATC

Prérequis

  • A basic understanding of microprocessors and microcontrollers is recommended
  • A basic understanding of digital logic or hardware / ASIC design issues would be useful but not essential
  • A basic understanding of assembler or C programming would be useful but not essential

Contenu

Clarifying the internal data paths : AHB bus, peripheral buses

Highlighting the purpose of the 2 central interconnect units : MAX and M3IF

Organization of a board based on i.MX31

Presentation of the core, architecture and programming model

Operating modes : user, system, super, IRQ, FIQ, undef and abort

ARM vs Thumb instruction sets, interworking

Branch instructions, implementation of C call and return statements

Level1 cache operation

Memory management unit

C-to-Assembly interface

Exception mechanism, handler table

Debug facilities

Clock distribution

PLL output frequency calculation

Power-up sequence

Low power modes, clock gating

Global reset vs warm reset

System boot mode selection

GPIO module

General Purpose Input interrupt request capability

Signal description

MAX parameterizing

ARM Vector Interrupt Controller

Level 2 cache operation

Scheduler

CRC calculation unit

SDMA initialisation

Instruction description

Description of the Master Arbitration and Buffering [MAB] unit

Description of the M3IF arbitration [M3A]

Introduction to DDR SDRAM

Enhanced DDR SDRAM controller

NAND flash controller, boot from flash

ATA controller

MSHC

SDHC

Video acquisition

MPEG4 encoder

Image Processing Unit

Graphics accelerator

SSI interfaces

Digital audio multiplexer

1-wire interface

Configurable SPI

I2C interfaces

UART

USB

Introducing the tools required to generate the kernel image

What is required on the host before installing LTIB

Common package selection screen

Common target system configuration screen

Building a complete BSP with the default configurations

Creating a Root Filesystems image

Re-configuring the kernel under LTIB

Selecting user-space packages

Setup the bootloader arguments to use the exported RFS

Debugging Uboot and the kernel by using Trace32

Command line options

Adding a new package

Other deployment methods

Creating a new package and integrating it into LTIB

A lot of labs have been created to explain the usage of LTIB

Notes

  • Les supports de cours seront fournis sur papier à chaque participant pendant la formation