Vivado™ Design Suite : Partial Reconfiguration

(ref.004873A)

2 days

Objectives

  • Build and assemble a Partially Reconfigurable (PR) system
  • Define PR regions and reconfigurable modules with the Vivado™ Design Suite
  • Generate the appropriate full and partial bitstreams for PR design
  • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
  • Implement a PR system using the following techniques
    • Direct JTAG connection
    • Timing constraints and analysis
    • Floorplanning

Partners

xilinx atp

Prerequisites

  • Intermediate knowledge in HDL language and a good experience with the Vivado™ Design suite and FPGAs
  • Vivado™ Design Suite : Static Timing Analysis (STA) and Xilinx Design Constraints (XDC) training (004913A) or equivalent knowledge
  • Vivado™ Design Suite : Advanced Tools and Techniques training (004914A) or equivalent knowledge
  • Knowledge/experience with the basics of the TCL language

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design Suite 2016.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080
  • On Site training : video projector

Outline

Partial Reconfiguration Overview

PR Terminology

PR Design Flow

Lab : Partial Reconfiguration Flow

PR Tool Flow Details

Design Requirements and Guidelines

Design Recommendations

PR Tool Flow Recommendations

Lab : Floorplanning

Bitstream Integrity

ICAP Silicon Resource

Timing

Timing Constraints

Timing Analysis

Lab : Partial Reconfiguration Timing Analysis and Constraints

Notes

  • Training manuals will be given to attendees during training in print.