Designing with the Xilinx™ 7-Series Families
- Learn how to effectively use Xilinx 7 series (Artix-7, Kintex-7 and Virtex-7) architectural resources.
- Understand the CLBs and different type of slices structure.
- Understand clocks resources (MMCM, PLL and also global, horizontal, regional and IO clocks).
- Design effectively with block RAM and block DSP.
- Effectively use I/O blocks especially with SERDES blocks.
- Know the memory controllers
- Proper VHDL coding techniques.
- Introduction to the integrated hardware resources (Multi-Gigabit Transceivers, PCI-e and XADC)
- Basic knowledge FPGAs architectures
- A successful first experience of designing an VHDL–based FPGA
- Software Configuration :
- Xilinx Vivado™ Logic Edition 2014.3
- Hardware configuration:
- Recent computer (i5 or i7)
- Windows XP or 7
- At least 4GB RAM
- Minimum display resolution 1024 x 768
- On Site training : video projector
7 series family overview
CLB and Slices architecture
Clocking Resources and management
Introduction to dedicated resources (MGT, PCI-e and XADC)
- Training manuals will be given to attendees during training in print.