Essential DSP implementation techniques for AMD FPGAs

(ref.D_ESS)

2 days - 14 hours

Objectives

  • After completing this training, you will have the necessary skills to:
    • 1 - Describe the advantages of using FPGAs over traditional processors for DSP designs, utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
    • 2 - Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
    • 3 - Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
    • 4 - Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA

Prerequisites

  • Fundamental understanding of digital signal processing theory and an appreciation of the principles of the following :
    • Sample rates
    • FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filters
    • Oscillators and Mixers
    • FFT (Fast Fourier Transform) algorithm

Concerned public

  • Technicians and Engineers in Digital Electronics
  • All our training courses are given at a distance and are accessible to people with reduced mobility.
  • Our partner AGEFIPH accompanies us to implement the necessary adaptations related to your disability.
              • agefiph

Notes

  • Release date: 03/08/2023

Chapters

Day 1

Objective 1

  • Back to basics {Lecture}

Objective 2

  • Architecture of FPGAs {Lecture}
  • Mathematics of FPGAs {Lecture, Lab}

Objective 3

  • Shift registers, memory and application {Lecture, Lab}

Objective 4

  • The FIR filter {Lecture, Lab}

Day 2

Objective 4

  • Advanced filtering techniques {Lecture, Lab}
  • The Fast Fourier Transform {Lecture, Lab}

Teaching Methods

  • Inter-company online training :
    • Presentation by Webex by Cisco
              • Webex de Cisco
    • Provision of course material in PDF format
    • Labs on Cloud PC by RealVNC
              • REALVNC

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Support

  • Authorized Trainer Provider AMD : Engineer Electronics and Telecommunications ENSIL
    • Expert AMD FPGA - Language VHDL/Verilog - RTL Design
    • Expert AMD SoC & MPSoC - Language C/C++ - System Design
    • Expert DSP & AMD RFSoC – HLS - Matlab - Design DSP RF
    • Expert AMD Versal – AI Engines – Heteregenous System Architect

PC Recommended

Partner

xilinx atp