VHDL Logical Synthesis and Simulation for Xilinx™ FPGA design

(ref.002572A)

5 days

Objectives

  • Comprehend the various possibilities offered by VHDL language
  • Understand the logical synthesis notions
  • Knowing the different writing style and their impact on the quality of synthesis results
  • Knowing the performance that can be expected from Xilinx FPGA
  • Learning how to configure compilation options and implementation constraints
  • Manipulating the debug tools and implementation reports

Partners

xilinx atp

Prerequisites

  • This training is intended to electronic engineers who already have a good knowledge in designing digital electronic circuits, who are willing to acquire a strong designing methodology, and to take the best of VHDL language and the associated synthesis and simulation tools for designing Xilinx FPGA.

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Logic Edition 2015.x
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080
  • On Site training : video projector

Outline

Spartan3A, Spartan6, Virtex5, Virtex6 and 7-Series FPGA architecture

  • General structure
  • CLB and slices notion
    • Combinatory logic and registers
    • Arithmetical logic
    • Distributed memory
    • Shift register SRL
  • In/Out blocks
    • In/Out registers
    • DDR registers
    • timing and electric settings and specificities
  • Dedicated RAM blocks and use modes
    • Customable FIFOs implementation
    • Other example of use
  • Clocks distribution, DCMs and PLLs
    • Global Buffer, local buffer
    • DCMs, PLLs and settings
  • Dedicated multipliers and DSP48 blocks
  • Configuration
    • Master, slave, SPI, BPI, JTAG

Writing rules of VHDL code in logical synthesis

  • Notion of entity / architecture
  • Concurrent and sequential instructions
  • Predefined types and objects
  • Predefined operators and of use extended by using standardized packages
  • Concurrent instructions : when, with select, for generate
  • Practical labs

Writing rules of VHDL code in logical synthesis (next)

  • Process
    • Importance of the sensitivity list
    • Sequential instructions : if, case, loop
    • Use of variables
    • A few tricks to avoid
    • Potential interpretation incoherencies between the logical synthesis and the simulation : how to avoid it

Hierarchy management for a better use

  • Organization of design by functional modules : what routing to choose ?
  • Inference and instancing notions
    • When is it important to instantiate primitives or macros ?
  • Precautions for an evolutionary and / or re-usable code
  • Importance of module’s name selection and of the nets to facilitate the physical implementation, the simulation and the tuning
  • Does the hierarchy have to be preserved during the logical synthesis ?
  • Practical labs

Advanced VHDL language for optimization and code re-use in logical synthesis

  • Notion of variable and example of use
  • Genericity and automatic configuration of re-usable modules
  • Useful predefined attributes in logical synthesis
  • Functions and procedures
  • Definition of packages and libraries
  • Practical labs

Hardware designing methodology in logical synthesis

  • Asynchronous conception and classic tricks
    • Metastability and hazards of functioning
    • Limits of functional simulation and timing on asynchronous designs : how to get over them?
  • Asynchronous event management
    • Random
    • Data streams
  • Synchronous design
  • Static timing analysis : how to use it?
  • Optimization of performance irrespective of the target
  • Pipeline notion
  • Practical labs

Implementation and tuning tools

  • Implementation flow and bitstream generation
  • Reports Analysis
  • Main implementation options
  • Implementation results analysis tools

Test benches and simulation

  • A few basic rules for the writing of an efficient testbench
  • VHDL instructions specific to simulation
    • Wait and its various forms
    • Loop
    • Assertions
    • Data types
    • Others
  • Writing components models intended to make the simulation more realistic
  • Use of existing models and simulation packages
  • Practical labs
  • Writing and reading of ASCII files
    • Allocation of a data flow from a file
    • Storage of the simulation results in a file
    • Command interpreter
  • Generating information messages
  • Practical labs

Notes

  • Training manuals will be given to attendees during training in print.