SDSoC Development Environment and Methodology


1 day


  • Anyone interested in quickly adding hardware acceleration to a software system should attend this training.
    • Identify candidate functions for hardware acceleration by using the TCF profiling tool
    • Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
    • Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
    • Override tool defaults to improve the performance of the individual accelerators and the overall system


xilinx atp


  • C or C++ Knowledge
  • Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK
  • Understanding of Zynq®-7000 architecture (with emphasis on ACP or HP)


  • Software Configuration :
    • Xilinx SDSoC Environment 2015.4
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080
  • On Site training : video projector


Course Introduction

SDSoC Tool Overview {Lecture, Demos, Lab}

SDSoC Design Best Practices {Lecture, Demo}

Profiling {Lecture, Demo, Lab}

Debugging {Lecture, Demo, Lab}

Understanding Estimations {Lecture, Demo, Lab}

Blocking vs. Non-Blocking Implementations {Lecture, Lab}

Multiple Accelerators {Lecture, Lab}


  • Training manuals will be given to attendees during training in print.