Vivado™ Design Suite for ISE® Software Project Navigator Users

(ref.F_V4ISE)

2 days - 14 hours

Objectives

  • This course offers introductory training on the Vivado™ Design Suite. This course is for experienced ISE® software users who want to take full advantage of the Vivado™ Design Suite feature set.
    • Use the Project Manager to start a new project.
    • Identify the Vivado™ IDE design flows (project based and non-project batch).
    • Identify file sets (HDL, XDC, simulation).
    • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer.
    • Synthesize and implement an HDL design
    • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
    • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Partners

xilinx atp

Prerequisites

  • Intermediate knowledge in HDL language and some experience with the Xilinx ISE® design suite tools and FPGAs.
  • Knowledge/experience with the basics of the TCL language.

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design or System Edition 2017.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

UltraFast Design Methodology: Planning {Lecture}

UltraFast Design Methodology: Design Creation and Analysis {Lecture}

HDL Coding Techniques {Lecture}

Resets {Lecture, Lab}

Register Duplication {Lecture}

Synchronous Design Techniques {Lecture}

Introduction to the Vivado Design Suite {Lecture}

Introduction to Vivado Design Flows {Lecture}

Vivado Design Suite Project Mode {Lectures, Lab}

Synthesis and Implementation {Lecture, Lab}

Basic Design Analysis in the Vivado IDE {Lab}

Vivado Design Suite I/O Pin Planning {Lecture, Lab}

Vivado IP Flow {Lecture, Lab, Demo}

Designing with IP Integrator {Lecture, Lab}

Vivado Design Suite Non-Project Mode {Lecture}

Introduction to the Tcl Environment {Lecture, Lab}

Design Analysis Using Tcl Commands {Lecture, Lab}

Scripting in Vivado Design Suite Project Mode {Lecture}

Scripting in Vivado Design Suite Non-Project Mode {Lecture}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics