Vivado™ Design Suite : Partial Reconfiguration

(ref.F_PR)

2 days - 14 hours

Objectives

  • After completing this comprehensive training, you will have the necessary skills to:
    • Build and assemble a Partially Reconfigurable (PR) system
    • Define PR regions and reconfigurable modules with the Vivado™ Design Suite
    • Generate the appropriate full and partial bitstreams for PR design
    • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
    • Implement a PR system using the following techniques
      • Direct JTAG connection
      • Timing constraints and analysis
      • Floorplanning
    • Implement a PR system using the PRC IP
    • Implement a PR system in an embedded environment
    • Debug PR designs

Partners

xilinx atp

Prerequisites

  • Intermediate knowledge in HDL language and a good experience with the Vivado™ Design suite and FPGAs
  • Vivado™ Design Suite : Static Timing Analysis (STA) and Xilinx Design Constraints (XDC) training (F_STAXDC) or equivalent knowledge
  • Vivado™ Design Suite : Advanced Tools and Techniques training (F_VATT) or equivalent knowledge
  • Knowledge/experience with the basics of the TCL language

Configurations

  • Software Configuration :
    • Xilinx Vivado™ Design Suite 2017.1
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Partial Reconfiguration Methodology

Partial Reconfiguration Tool Flow

Lab 1: Partial Reconfiguration Flow

Lab 2: Floorplanning the PR Design

FPGA Configuration Overview

Partial Reconfiguration Bitstreams

Lab 3: Using the Partial Reconfiguration Controller in a PR Design

Managing Clocks, I/Os, and GTs

Partial Reconfiguration: Managing Timing

Lab 4: Partial Reconfiguration Timing Analysis and Constraints

Partial Reconfiguration in Embedded Systems

Lab 5: Partial Reconfiguration in Embedded Systems

Debugging Partial Reconfiguration Designs

Lab 6: Debugging a Partial Reconfiguration Design

Partial Reconfiguration Design Recommendations

PCIe Core and Partial Reconfiguration

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives