Zynq UltraScale+™ All Programmable MPSoC : Hardware and Software Design

(ref.E_ZUPSW)

2 days - 14 hours

Objectives

  • This course provides software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq® UltraScale+™ MPSoC family.
  • After completing this comprehensive training, you will have the necessary skills to:
    • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
    • List the various power domains and how they are controlled
    • Describe the connectivity between the processing system (PS) and programmable logic (PL)
    • Utilize QEMU to emulate hardware behavior
    • Distinguish between asymmetric multi-processing (AMP) and symmetric multi-processing (SMP) environments
    • Identify situations when the ARM® TrustZone technology and/or a hypervisor should be used
    • Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)
    • Define the boot sequences appropriate to the needs of the system
    • Define the underlying implementation of the application processing unit (APU) and real-time processing unit (RPU) to make best use of their capabilities

Partners

xilinx atp

Prerequisites

  • General understanding of embedded and real-time operating systems
  • Familiarity with issues related to implementing a complex embedded system

Configurations

  • Software Configuration :
    • Vivado® Design Suite 2017.3 (May require special Zynq UltraScale+ MPSoC family license)
  • Hardware emulation environment :
    • VirtualBox
    • QEMU
    • Ubuntu desktop
    • PetaLinux
  • Hardware configuration:
    • Recent computer (i5 or i7)
    • Windows 7 64b
    • At least 8GB RAM
    • Minimum display resolution 1024 x 768, recommended 1920x1080

Outline

Zynq UltraScale+ MPSoC Application Processing Unit {Lecture, Lab}

Zynq UltraScale+ MPSoC Real-Time Processing Unit {Lecture, Lab}

QEMU {Lecture, Lab}

Zynq UltraScale+ MPSoC HW-SW Virtualization {Lecture, Lab}

Zynq UltraScale+ MPSoC Booting {Lecture, Lab}

Zynq UltraScale+ MPSoC System Protection {Lecture}

Zynq UltraScale+ MPSoC Clocks and Resets {Lecture}

Zynq UltraScale+ MPSoC PMU {Lecture, Lab}

ARM TrustZone Technology {Lecture}

MultiProcessor Software Architecture {Lecture}

Xen Hypervisor {Lecture, Lab} (pairs with OpenAMP, but not SMP)

OpenAMP {Lecture, Lab} (pairs with the Xen Hypervisor, but not SMP)

Linux {Lecture}

Yocto {Lecture, Lab}

Open Source Library (Linux) {Lecture, Lab}

FreeRTOS {Lecture, Lab}

Zynq UltraScale+ MPSoC Software Stack {Lecture}

Teaching Methods

  • Face to face
  • Presentation by video projector
  • Provision of paper-based course materials

Support

  • Authorized Trainer Provider XILINX : Engineer Electronics and Telecommunications ENSIL
    • Expert FPGA XILINX - Language VHDL - DSP - Design RTL

Methods of monitoring and assessment of results

  • Attendance sheet
  • Evaluation questionnaire
  • Evaluation sheet on:
    • Technical questionnaire
    • Result of the Practical Works
    • Validation of Objectives
  • Presentation of a certificate with assessment of prior learning

Concerned public

  • Technicians and Engineers in Digital Electronics