ARM Cortex A57 - System design


4 days - 28 hours


  • This course takes an in depth look at the considerations you will need to take into account when designing a system containing a Cortex-A57 processor core
  • It is aimed at :
    • Software engineers who not only want to obtain details of how to write software to run on the Cortex-A57, but also wish to obtain an understanding of hardware design issues
    • Hardware engineers who need to understand how to design Cortex-A57 based systems, but also wish to obtain an understanding of the issues of writing software to run on that system




  • A basic understanding of microprocessors and microcontrollers is recommended
  • A basic understanding of digital logic or hardware / ASIC design issues would be useful but not essential
  • A basic understanding of assembler or C programming would be useful but not essential
  • A basic awareness ARM cores is useful but not essential


Hardware configuration options

Software support

Architecture versions

Privilege levels

AArch64 registers

A64 instruction set

AArch64 exception model

AArch64 memory model

Register set

Load/Store instructions

Data processing instructions

Program flow instructions

System control

Advanced SIMD

Cryptographic extensions

The AArch64 exception model


Synchronous exceptions

SError exceptions

SError exceptions in EL2 and EL3

Memory management theory

Stage 1 translations at EL 1/0

  • Kernel/application space translation tables

translations at EL2/EL3

  • Stage 1 tables for hypervisor/secure exception levels
  • Stage 2 tables for virtualized systems

TLB maintenance



Alignment & endianess

General cache information

Cache attributes

Cache maintenance operations

Cache discovery

Data barriers

Instruction barriers

Synchronisation in ARMv8-A

Local and Global exclusive monitors

Introduction to coherency

Coherency details - multi-core processors

Coherency details - multi-processor systems

Context switching

Modifying translation tables

Privilege escalation protections



Interrupt configuration

Booting a Cortex-A5x processor in AArch64

Processor setup

Power overview

Processor Power Modes

Multiprocessor and System Power Mode

Cortex-A5 and Cortex-A9 Power Mode

What is virtualization ?

ARM virtualization support

  • Memory management
  • Exception handling

Introduction to SMMU

Software stack

Memory system


TBSA (Trusted Base System Architecture)

Distributor and CPU interfaces

How to enable and configure interrupts

How to handle interrupts

How to send software interrupts

Security extensions

Debug infrastructure

Invasive debug

Non-invasive debug