ARM Cortex A17/A15/A7 - System design

(ref.005008A)

4 days - 28 hours

Objectives

  • This course takes an in depth look at the considerations you will need to take into account when designing a system containing a Cortex- A17/A15/A7 processor core
  • It is aimed at :
    • Software engineers who not only want to obtain details of how to write software to run on the Cortex- A17/A15/A7, but also wish to obtain an understanding of hardware design issues
    • Hardware engineers who need to understand how to design Cortex- A17/A15/A7 based systems, but also wish to obtain an understanding of the issues of writing software to run on that system

Partners

ARM ATC

Prerequisites

  • A basic understanding of microprocessors and microcontrollers is recommended
  • A basic understanding of digital logic or hardware / ASIC design issues would be useful but not essential
  • A basic understanding of assembler or C programming would be useful but not essential
  • A basic awareness ARM cores is useful but not essential

Outline

Architecture versions

Registers and instruction sets

Exception model

Memory model

Coprocessors

Architecture extensions

The future

Introduction

New features in Cortex-A17 / Cortex-A15 / Cortex-A7

Big/Little processing

Caches in Cortex-A

Level 2 caches

Cache Policies

Branch prediction

What is a MMU ?

Short-descriptor format

Long-descriptor format

Memory types and attributes

Using the MMU

Overview

Exception handling

Memory system

Debug

Software

The need of atomicity

LDREX and STREX instructions

Multi-thread MUTEX example

Distributor and CPU interfaces

How to enable and configure interrupts

How to handle interrupts

How to send software interrupts

Security extensions

Power Overview

Processor Power Modes

Multiprocessor and system Power Modes

Cortex-A5 and Cortex-A9 Power Modes

L1 & L2 cache coherency and maintenance

MPCore coherency

Multi-Processing

Translation tables

Context switching

Timers

Data barriers

Instruction barriers

Introduction

Multi-Cluster configurations

Miscellaneous considerations

Overview

Booting a single CPU

Booting a cluster

Invasive debug

Non-Invasive debug

  • PMU (Performance Monitoring Unit)
  • Trace

Parameter passing

Floating point linkage

Alignment

Coding considerations

Introduction

NEON instruction set overview

NEON Software Support

Overview of virtualization extensions

Memory management

Exception handling

Notes

  • Training manuals will be given to attendees during training in print